1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Cross Bar Switch Internal Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CROSSBAR_H__ 11*4882a593Smuzhiyun #define __CROSSBAR_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /********************************************************************* 14*4882a593Smuzhiyun * Cross-bar switch (XBS) 15*4882a593Smuzhiyun *********************************************************************/ 16*4882a593Smuzhiyun typedef struct xbs { 17*4882a593Smuzhiyun u32 prs1; /* 0x100 Priority Register Slave 1 */ 18*4882a593Smuzhiyun u32 res1[3]; /* 0x104 - 0F */ 19*4882a593Smuzhiyun u32 crs1; /* 0x110 Control Register Slave 1 */ 20*4882a593Smuzhiyun u32 res2[187]; /* 0x114 - 0x3FF */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun u32 prs4; /* 0x400 Priority Register Slave 4 */ 23*4882a593Smuzhiyun u32 res3[3]; /* 0x404 - 0F */ 24*4882a593Smuzhiyun u32 crs4; /* 0x410 Control Register Slave 4 */ 25*4882a593Smuzhiyun u32 res4[123]; /* 0x414 - 0x5FF */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun u32 prs6; /* 0x600 Priority Register Slave 6 */ 28*4882a593Smuzhiyun u32 res5[3]; /* 0x604 - 0F */ 29*4882a593Smuzhiyun u32 crs6; /* 0x610 Control Register Slave 6 */ 30*4882a593Smuzhiyun u32 res6[59]; /* 0x614 - 0x6FF */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun u32 prs7; /* 0x700 Priority Register Slave 7 */ 33*4882a593Smuzhiyun u32 res7[3]; /* 0x704 - 0F */ 34*4882a593Smuzhiyun u32 crs7; /* 0x710 Control Register Slave 7 */ 35*4882a593Smuzhiyun } xbs_t; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Bit definitions and macros for PRS group */ 38*4882a593Smuzhiyun #define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */ 39*4882a593Smuzhiyun #define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */ 40*4882a593Smuzhiyun #define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */ 41*4882a593Smuzhiyun #define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */ 42*4882a593Smuzhiyun #define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */ 43*4882a593Smuzhiyun #define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */ 44*4882a593Smuzhiyun #define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Bit definitions and macros for CRS group */ 47*4882a593Smuzhiyun #define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */ 48*4882a593Smuzhiyun #define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */ 49*4882a593Smuzhiyun #define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */ 50*4882a593Smuzhiyun #define XBS_CRS_RO (0x80000000) /* Read Only */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_FIELD (0) 53*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_ON_LAST (1) 54*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_NONE (2) 55*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_CORE (0) 56*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_EDMA (1) 57*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_FEC0 (2) 58*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_FEC1 (3) 59*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_PCI (5) 60*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_USB (6) 61*4882a593Smuzhiyun #define XBS_CRS_PCTL_PARK_SBF (7) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* __CROSSBAR_H__ */ 64