1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/timer.h>
11*4882a593Smuzhiyun #include <asm/immap.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static ulong timestamp;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #if defined(CONFIG_SLTTMR)
19*4882a593Smuzhiyun #ifndef CONFIG_SYS_UDELAY_BASE
20*4882a593Smuzhiyun # error "uDelay base not defined!"
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
24*4882a593Smuzhiyun # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun extern void dtimer_intr_setup(void);
27*4882a593Smuzhiyun
__udelay(unsigned long usec)28*4882a593Smuzhiyun void __udelay(unsigned long usec)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
31*4882a593Smuzhiyun u32 now, freq;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* 1 us period */
34*4882a593Smuzhiyun freq = CONFIG_SYS_TIMER_PRESCALER;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Disable */
37*4882a593Smuzhiyun out_be32(&timerp->cr, 0);
38*4882a593Smuzhiyun out_be32(&timerp->tcnt, usec * freq);
39*4882a593Smuzhiyun out_be32(&timerp->cr, SLT_CR_TEN);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun now = in_be32(&timerp->cnt);
42*4882a593Smuzhiyun while (now != 0)
43*4882a593Smuzhiyun now = in_be32(&timerp->cnt);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun setbits_be32(&timerp->sr, SLT_SR_ST);
46*4882a593Smuzhiyun out_be32(&timerp->cr, 0);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
dtimer_interrupt(void * not_used)49*4882a593Smuzhiyun void dtimer_interrupt(void *not_used)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* check for timer interrupt asserted */
54*4882a593Smuzhiyun if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
55*4882a593Smuzhiyun setbits_be32(&timerp->sr, SLT_SR_ST);
56*4882a593Smuzhiyun timestamp++;
57*4882a593Smuzhiyun return;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
timer_init(void)61*4882a593Smuzhiyun int timer_init(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun timestamp = 0;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* disable timer */
68*4882a593Smuzhiyun out_be32(&timerp->cr, 0);
69*4882a593Smuzhiyun out_be32(&timerp->tcnt, 0);
70*4882a593Smuzhiyun /* clear status */
71*4882a593Smuzhiyun out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* initialize and enable timer interrupt */
74*4882a593Smuzhiyun irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Interrupt every ms */
77*4882a593Smuzhiyun out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun dtimer_intr_setup();
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* set a period of 1us, set timer mode to restart and
82*4882a593Smuzhiyun enable timer and interrupt */
83*4882a593Smuzhiyun out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
get_timer(ulong base)87*4882a593Smuzhiyun ulong get_timer(ulong base)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun return (timestamp - base);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #endif /* CONFIG_SLTTMR */
93