1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * (C) Copyright 2000-2003
4*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <watchdog.h>
14*4882a593Smuzhiyun #include <command.h>
15*4882a593Smuzhiyun #include <netdev.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/immap.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
21*4882a593Smuzhiyun
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])22*4882a593Smuzhiyun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun out_be16(&gptmr->pre, 10);
27*4882a593Smuzhiyun out_be16(&gptmr->cnt, 1);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* enable watchdog, set timeout to 0 and wait */
30*4882a593Smuzhiyun out_8(&gptmr->mode, GPT_TMS_SGPIO);
31*4882a593Smuzhiyun out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* we don't return! */
34*4882a593Smuzhiyun return 1;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
checkcpu(void)37*4882a593Smuzhiyun int checkcpu(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun siu_t *siu = (siu_t *) MMAP_SIU;
40*4882a593Smuzhiyun u16 id = 0;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun puts("CPU: ");
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
45*4882a593Smuzhiyun case 0x0C:
46*4882a593Smuzhiyun id = 5485;
47*4882a593Smuzhiyun break;
48*4882a593Smuzhiyun case 0x0D:
49*4882a593Smuzhiyun id = 5484;
50*4882a593Smuzhiyun break;
51*4882a593Smuzhiyun case 0x0E:
52*4882a593Smuzhiyun id = 5483;
53*4882a593Smuzhiyun break;
54*4882a593Smuzhiyun case 0x0F:
55*4882a593Smuzhiyun id = 5482;
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun case 0x10:
58*4882a593Smuzhiyun id = 5481;
59*4882a593Smuzhiyun break;
60*4882a593Smuzhiyun case 0x11:
61*4882a593Smuzhiyun id = 5480;
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun case 0x12:
64*4882a593Smuzhiyun id = 5475;
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun case 0x13:
67*4882a593Smuzhiyun id = 5474;
68*4882a593Smuzhiyun break;
69*4882a593Smuzhiyun case 0x14:
70*4882a593Smuzhiyun id = 5473;
71*4882a593Smuzhiyun break;
72*4882a593Smuzhiyun case 0x15:
73*4882a593Smuzhiyun id = 5472;
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun case 0x16:
76*4882a593Smuzhiyun id = 5471;
77*4882a593Smuzhiyun break;
78*4882a593Smuzhiyun case 0x17:
79*4882a593Smuzhiyun id = 5470;
80*4882a593Smuzhiyun break;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (id) {
84*4882a593Smuzhiyun char buf1[32], buf2[32];
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun printf("Freescale MCF%d\n", id);
87*4882a593Smuzhiyun printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
88*4882a593Smuzhiyun strmhz(buf1, gd->cpu_clk),
89*4882a593Smuzhiyun strmhz(buf2, gd->bus_clk));
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #if defined(CONFIG_HW_WATCHDOG)
96*4882a593Smuzhiyun /* Called by macro WATCHDOG_RESET */
hw_watchdog_reset(void)97*4882a593Smuzhiyun void hw_watchdog_reset(void)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun out_8(&gptmr->ocpw, 0xa5);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
watchdog_disable(void)104*4882a593Smuzhiyun int watchdog_disable(void)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
109*4882a593Smuzhiyun out_8(&gptmr->mode, 0);
110*4882a593Smuzhiyun out_8(&gptmr->ctrl, 0);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun puts("WATCHDOG:disabled\n");
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return (0);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
watchdog_init(void)117*4882a593Smuzhiyun int watchdog_init(void)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
122*4882a593Smuzhiyun out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun out_8(&gptmr->mode, GPT_TMS_SGPIO);
125*4882a593Smuzhiyun out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
126*4882a593Smuzhiyun puts("WATCHDOG:enabled\n");
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return (0);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun #endif /* CONFIG_HW_WATCHDOG */
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
133*4882a593Smuzhiyun /* Default initializations for MCFFEC controllers. To override,
134*4882a593Smuzhiyun * create a board-specific function called:
135*4882a593Smuzhiyun * int board_eth_init(bd_t *bis)
136*4882a593Smuzhiyun */
137*4882a593Smuzhiyun
cpu_eth_init(bd_t * bis)138*4882a593Smuzhiyun int cpu_eth_init(bd_t *bis)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun #if defined(CONFIG_FSLDMAFEC)
141*4882a593Smuzhiyun mcdmafec_initialize(bis);
142*4882a593Smuzhiyun #endif
143*4882a593Smuzhiyun #if defined(CONFIG_MCFFEC)
144*4882a593Smuzhiyun mcffec_initialize(bis);
145*4882a593Smuzhiyun #endif
146*4882a593Smuzhiyun return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun #endif
149