xref: /OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf5445x/cpu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * (C) Copyright 2000-2003
4*4882a593Smuzhiyun  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <watchdog.h>
14*4882a593Smuzhiyun #include <command.h>
15*4882a593Smuzhiyun #include <netdev.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <asm/immap.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
21*4882a593Smuzhiyun 
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])22*4882a593Smuzhiyun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun 	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
25*4882a593Smuzhiyun 	udelay(1000);
26*4882a593Smuzhiyun 	out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
27*4882a593Smuzhiyun 	udelay(10000);
28*4882a593Smuzhiyun 	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	/* we don't return! */
31*4882a593Smuzhiyun 	return 0;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
checkcpu(void)34*4882a593Smuzhiyun int checkcpu(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	ccm_t *ccm = (ccm_t *) MMAP_CCM;
37*4882a593Smuzhiyun 	u16 msk;
38*4882a593Smuzhiyun 	u16 id = 0;
39*4882a593Smuzhiyun 	u8 ver;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	puts("CPU:   ");
42*4882a593Smuzhiyun 	msk = (in_be16(&ccm->cir) >> 6);
43*4882a593Smuzhiyun 	ver = (in_be16(&ccm->cir) & 0x003f);
44*4882a593Smuzhiyun 	switch (msk) {
45*4882a593Smuzhiyun 	case 0x48:
46*4882a593Smuzhiyun 		id = 54455;
47*4882a593Smuzhiyun 		break;
48*4882a593Smuzhiyun 	case 0x49:
49*4882a593Smuzhiyun 		id = 54454;
50*4882a593Smuzhiyun 		break;
51*4882a593Smuzhiyun 	case 0x4a:
52*4882a593Smuzhiyun 		id = 54453;
53*4882a593Smuzhiyun 		break;
54*4882a593Smuzhiyun 	case 0x4b:
55*4882a593Smuzhiyun 		id = 54452;
56*4882a593Smuzhiyun 		break;
57*4882a593Smuzhiyun 	case 0x4d:
58*4882a593Smuzhiyun 		id = 54451;
59*4882a593Smuzhiyun 		break;
60*4882a593Smuzhiyun 	case 0x4f:
61*4882a593Smuzhiyun 		id = 54450;
62*4882a593Smuzhiyun 		break;
63*4882a593Smuzhiyun 	case 0x9F:
64*4882a593Smuzhiyun 		id = 54410;
65*4882a593Smuzhiyun 		break;
66*4882a593Smuzhiyun 	case 0xA0:
67*4882a593Smuzhiyun 		id = 54415;
68*4882a593Smuzhiyun 		break;
69*4882a593Smuzhiyun 	case 0xA1:
70*4882a593Smuzhiyun 		id = 54416;
71*4882a593Smuzhiyun 		break;
72*4882a593Smuzhiyun 	case 0xA2:
73*4882a593Smuzhiyun 		id = 54417;
74*4882a593Smuzhiyun 		break;
75*4882a593Smuzhiyun 	case 0xA3:
76*4882a593Smuzhiyun 		id = 54418;
77*4882a593Smuzhiyun 		break;
78*4882a593Smuzhiyun 	}
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	if (id) {
81*4882a593Smuzhiyun 		char buf1[32], buf2[32], buf3[32];
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
84*4882a593Smuzhiyun 		       ver);
85*4882a593Smuzhiyun 		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
86*4882a593Smuzhiyun 		       strmhz(buf1, gd->cpu_clk),
87*4882a593Smuzhiyun 		       strmhz(buf2, gd->bus_clk),
88*4882a593Smuzhiyun 		       strmhz(buf3, gd->arch.flb_clk));
89*4882a593Smuzhiyun #ifdef CONFIG_PCI
90*4882a593Smuzhiyun 		printf("       PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
91*4882a593Smuzhiyun 		       strmhz(buf1, gd->pci_clk),
92*4882a593Smuzhiyun 		       strmhz(buf2, gd->arch.inp_clk),
93*4882a593Smuzhiyun 		       strmhz(buf3, gd->arch.vco_clk));
94*4882a593Smuzhiyun #else
95*4882a593Smuzhiyun 		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
96*4882a593Smuzhiyun 		       strmhz(buf1, gd->arch.inp_clk),
97*4882a593Smuzhiyun 		       strmhz(buf2, gd->arch.vco_clk));
98*4882a593Smuzhiyun #endif
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #if defined(CONFIG_MCFFEC)
105*4882a593Smuzhiyun /* Default initializations for MCFFEC controllers.  To override,
106*4882a593Smuzhiyun  * create a board-specific function called:
107*4882a593Smuzhiyun  * 	int board_eth_init(bd_t *bis)
108*4882a593Smuzhiyun  */
109*4882a593Smuzhiyun 
cpu_eth_init(bd_t * bis)110*4882a593Smuzhiyun int cpu_eth_init(bd_t *bis)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	return mcffec_initialize(bis);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun #endif
115