1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * (C) Copyright 2000-2003
4*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <watchdog.h>
14*4882a593Smuzhiyun #include <command.h>
15*4882a593Smuzhiyun #include <netdev.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/immap.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
21*4882a593Smuzhiyun
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])22*4882a593Smuzhiyun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun rcm_t *rcm = (rcm_t *) (MMAP_RCM);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun udelay(1000);
27*4882a593Smuzhiyun setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* we don't return! */
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
checkcpu(void)33*4882a593Smuzhiyun int checkcpu(void)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun ccm_t *ccm = (ccm_t *) MMAP_CCM;
36*4882a593Smuzhiyun u16 msk;
37*4882a593Smuzhiyun u16 id = 0;
38*4882a593Smuzhiyun u8 ver;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun puts("CPU: ");
41*4882a593Smuzhiyun msk = (in_be16(&ccm->cir) >> 6);
42*4882a593Smuzhiyun ver = (in_be16(&ccm->cir) & 0x003f);
43*4882a593Smuzhiyun switch (msk) {
44*4882a593Smuzhiyun #ifdef CONFIG_MCF5301x
45*4882a593Smuzhiyun case 0x78:
46*4882a593Smuzhiyun id = 53010;
47*4882a593Smuzhiyun break;
48*4882a593Smuzhiyun case 0x77:
49*4882a593Smuzhiyun id = 53012;
50*4882a593Smuzhiyun break;
51*4882a593Smuzhiyun case 0x76:
52*4882a593Smuzhiyun id = 53015;
53*4882a593Smuzhiyun break;
54*4882a593Smuzhiyun case 0x74:
55*4882a593Smuzhiyun id = 53011;
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun case 0x73:
58*4882a593Smuzhiyun id = 53013;
59*4882a593Smuzhiyun break;
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun #ifdef CONFIG_MCF532x
62*4882a593Smuzhiyun case 0x54:
63*4882a593Smuzhiyun id = 5329;
64*4882a593Smuzhiyun break;
65*4882a593Smuzhiyun case 0x59:
66*4882a593Smuzhiyun id = 5328;
67*4882a593Smuzhiyun break;
68*4882a593Smuzhiyun case 0x61:
69*4882a593Smuzhiyun id = 5327;
70*4882a593Smuzhiyun break;
71*4882a593Smuzhiyun case 0x65:
72*4882a593Smuzhiyun id = 5373;
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun case 0x68:
75*4882a593Smuzhiyun id = 53721;
76*4882a593Smuzhiyun break;
77*4882a593Smuzhiyun case 0x69:
78*4882a593Smuzhiyun id = 5372;
79*4882a593Smuzhiyun break;
80*4882a593Smuzhiyun case 0x6B:
81*4882a593Smuzhiyun id = 5372;
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun #endif
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (id) {
87*4882a593Smuzhiyun char buf1[32], buf2[32];
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
90*4882a593Smuzhiyun ver);
91*4882a593Smuzhiyun printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
92*4882a593Smuzhiyun strmhz(buf1, gd->cpu_clk),
93*4882a593Smuzhiyun strmhz(buf2, gd->bus_clk));
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #if defined(CONFIG_WATCHDOG)
100*4882a593Smuzhiyun /* Called by macro WATCHDOG_RESET */
watchdog_reset(void)101*4882a593Smuzhiyun void watchdog_reset(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Count register */
106*4882a593Smuzhiyun out_be16(&wdp->sr, 0x5555);
107*4882a593Smuzhiyun out_be16(&wdp->sr, 0xaaaa);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
watchdog_disable(void)110*4882a593Smuzhiyun int watchdog_disable(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
115*4882a593Smuzhiyun /* halted watchdog timer */
116*4882a593Smuzhiyun setbits_be16(&wdp->cr, WTM_WCR_HALTED);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun puts("WATCHDOG:disabled\n");
119*4882a593Smuzhiyun return (0);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
watchdog_init(void)122*4882a593Smuzhiyun int watchdog_init(void)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
125*4882a593Smuzhiyun u32 wdog_module = 0;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* set timeout and enable watchdog */
128*4882a593Smuzhiyun wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
129*4882a593Smuzhiyun #ifdef CONFIG_M5329
130*4882a593Smuzhiyun out_be16(&wdp->mr, wdog_module / 8192);
131*4882a593Smuzhiyun #else
132*4882a593Smuzhiyun out_be16(&wdp->mr, wdog_module / 4096);
133*4882a593Smuzhiyun #endif
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun out_be16(&wdp->cr, WTM_WCR_EN);
136*4882a593Smuzhiyun puts("WATCHDOG:enabled\n");
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun return (0);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun #endif /* CONFIG_WATCHDOG */
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #if defined(CONFIG_MCFFEC)
143*4882a593Smuzhiyun /* Default initializations for MCFFEC controllers. To override,
144*4882a593Smuzhiyun * create a board-specific function called:
145*4882a593Smuzhiyun * int board_eth_init(bd_t *bis)
146*4882a593Smuzhiyun */
147*4882a593Smuzhiyun
cpu_eth_init(bd_t * bis)148*4882a593Smuzhiyun int cpu_eth_init(bd_t *bis)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun return mcffec_initialize(bis);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun #endif
153