1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2003 3*4882a593Smuzhiyun * Josef Baumgartner <josef.baumgartner@telex.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * Hayden Fraser (Hayden.Fraser@freescale.com) 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/processor.h> 13*4882a593Smuzhiyun #include <asm/immap.h> 14*4882a593Smuzhiyun #include <asm/io.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ get_clocks(void)19*4882a593Smuzhiyunint get_clocks (void) 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun #if defined(CONFIG_M5208) 22*4882a593Smuzhiyun pll_t *pll = (pll_t *) MMAP_PLL; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun out_8(&pll->odr, CONFIG_SYS_PLL_ODR); 25*4882a593Smuzhiyun out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #if defined(CONFIG_M5249) || defined(CONFIG_M5253) 29*4882a593Smuzhiyun volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); 30*4882a593Smuzhiyun unsigned long pllcr; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef CONFIG_SYS_PLL_BYPASS 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #ifdef CONFIG_M5249 35*4882a593Smuzhiyun /* Setup the PLL to run at the specified speed */ 36*4882a593Smuzhiyun #ifdef CONFIG_SYS_FAST_CLK 37*4882a593Smuzhiyun pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ 38*4882a593Smuzhiyun #else 39*4882a593Smuzhiyun pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun #endif /* CONFIG_M5249 */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #ifdef CONFIG_M5253 44*4882a593Smuzhiyun pllcr = CONFIG_SYS_PLLCR; 45*4882a593Smuzhiyun #endif /* CONFIG_M5253 */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ 48*4882a593Smuzhiyun mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ 49*4882a593Smuzhiyun mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ 50*4882a593Smuzhiyun pllcr ^= 0x00000001; /* Set pll bypass to 1 */ 51*4882a593Smuzhiyun mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ 52*4882a593Smuzhiyun udelay(0x20); /* Wait for a lock ... */ 53*4882a593Smuzhiyun #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* CONFIG_M5249 || CONFIG_M5253 */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #if defined(CONFIG_M5275) 58*4882a593Smuzhiyun pll_t *pll = (pll_t *)(MMAP_PLL); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Setup PLL */ 61*4882a593Smuzhiyun out_be32(&pll->syncr, 0x01080000); 62*4882a593Smuzhiyun while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 63*4882a593Smuzhiyun ; 64*4882a593Smuzhiyun out_be32(&pll->syncr, 0x01000000); 65*4882a593Smuzhiyun while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 66*4882a593Smuzhiyun ; 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun gd->cpu_clk = CONFIG_SYS_CLK; 70*4882a593Smuzhiyun #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ 71*4882a593Smuzhiyun defined(CONFIG_M5271) || defined(CONFIG_M5275) 72*4882a593Smuzhiyun gd->bus_clk = gd->cpu_clk / 2; 73*4882a593Smuzhiyun #else 74*4882a593Smuzhiyun gd->bus_clk = gd->cpu_clk; 75*4882a593Smuzhiyun #endif 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C_FSL 78*4882a593Smuzhiyun gd->arch.i2c1_clk = gd->bus_clk; 79*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C2_FSL_OFFSET 80*4882a593Smuzhiyun gd->arch.i2c2_clk = gd->bus_clk; 81*4882a593Smuzhiyun #endif 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun return (0); 85*4882a593Smuzhiyun } 86