1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * (C) Copyright 2000-2003 4*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 7*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <asm/processor.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/immap.h> 16*4882a593Smuzhiyun #include <asm/io.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * get_clocks() fills in gd->cpu_clock and gd->bus_clk 21*4882a593Smuzhiyun */ get_clocks(void)22*4882a593Smuzhiyunint get_clocks(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun pll_t *pll = (pll_t *)(MMAP_PLL); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun out_be32(&pll->syncr, PLL_SYNCR_MFD(1)); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) 29*4882a593Smuzhiyun ; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun gd->bus_clk = CONFIG_SYS_CLK; 32*4882a593Smuzhiyun gd->cpu_clk = (gd->bus_clk * 2); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C_FSL 35*4882a593Smuzhiyun gd->arch.i2c1_clk = gd->bus_clk; 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun return (0); 39*4882a593Smuzhiyun } 40