1 /*
2 *
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <common.h>
13 #include <watchdog.h>
14 #include <asm/immap.h>
15 #include <asm/io.h>
16
17 #if defined(CONFIG_CMD_NET)
18 #include <config.h>
19 #include <net.h>
20 #include <asm/fec.h>
21 #endif
22
23 /* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
24 #ifdef CONFIG_M5235
25 #define out_be_fbcs_reg out_be16
26 #else
27 #define out_be_fbcs_reg out_be32
28 #endif
29
30 /*
31 * Breath some life into the CPU...
32 *
33 * Set up the memory map,
34 * initialize a bunch of registers,
35 * initialize the UPM's
36 */
cpu_init_f(void)37 void cpu_init_f(void)
38 {
39 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
40 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
41 wdog_t *wdog = (wdog_t *) MMAP_WDOG;
42 scm_t *scm = (scm_t *) MMAP_SCM;
43
44 /* watchdog is enabled by default - disable the watchdog */
45 #ifndef CONFIG_WATCHDOG
46 out_be16(&wdog->cr, 0);
47 #endif
48
49 out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
50
51 /* Port configuration */
52 out_8(&gpio->par_cs, 0);
53
54 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
55 out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
56 out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
57 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
58 #endif
59
60 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
61 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
62 out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
63 out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
64 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
65 #endif
66
67 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
68 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
69 out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
70 out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
71 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
72 #endif
73
74 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
75 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
76 out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
77 out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
78 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
79 #endif
80
81 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
82 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
83 out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
84 out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
85 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
86 #endif
87
88 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
89 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
90 out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
91 out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
92 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
93 #endif
94
95 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
96 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
97 out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
98 out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
99 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
100 #endif
101
102 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
103 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
104 out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
105 out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
106 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
107 #endif
108
109 #ifdef CONFIG_SYS_I2C_FSL
110 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
111 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
112 #endif
113
114 icache_enable();
115 }
116
117 /*
118 * initialize higher level parts of CPU like timers
119 */
cpu_init_r(void)120 int cpu_init_r(void)
121 {
122 return (0);
123 }
124
uart_port_conf(int port)125 void uart_port_conf(int port)
126 {
127 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
128
129 /* Setup Ports: */
130 switch (port) {
131 case 0:
132 clrbits_be16(&gpio->par_uart,
133 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
134 setbits_be16(&gpio->par_uart,
135 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
136 break;
137 case 1:
138 clrbits_be16(&gpio->par_uart,
139 GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
140 setbits_be16(&gpio->par_uart,
141 GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
142 break;
143 case 2:
144 #ifdef CONFIG_SYS_UART2_PRI_GPIO
145 clrbits_be16(&gpio->par_uart,
146 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
147 setbits_be16(&gpio->par_uart,
148 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
149 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
150 clrbits_8(&gpio->par_feci2c,
151 GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
152 setbits_8(&gpio->par_feci2c,
153 GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
154 #endif
155 break;
156 }
157 }
158
159 #if defined(CONFIG_CMD_NET)
fecpin_setclear(struct eth_device * dev,int setclear)160 int fecpin_setclear(struct eth_device *dev, int setclear)
161 {
162 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
163
164 if (setclear) {
165 setbits_8(&gpio->par_feci2c,
166 GPIO_PAR_FECI2C_EMDC_FECEMDC |
167 GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
168 } else {
169 clrbits_8(&gpio->par_feci2c,
170 GPIO_PAR_FECI2C_EMDC_MASK |
171 GPIO_PAR_FECI2C_EMDIO_MASK);
172 }
173
174 return 0;
175 }
176 #endif
177