1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * (C) Copyright 2000-2004 4*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 7*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* CPU specific interrupt routine */ 13*4882a593Smuzhiyun #include <common.h> 14*4882a593Smuzhiyun #include <asm/immap.h> 15*4882a593Smuzhiyun #include <asm/io.h> 16*4882a593Smuzhiyun interrupt_init(void)17*4882a593Smuzhiyunint interrupt_init(void) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Make sure all interrupts are disabled */ 22*4882a593Smuzhiyun setbits_be32(&intp->imrh0, 0xffffffff); 23*4882a593Smuzhiyun setbits_be32(&intp->imrl0, 0xffffffff); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun enable_interrupts(); 26*4882a593Smuzhiyun return 0; 27*4882a593Smuzhiyun } 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #if defined(CONFIG_MCFTMR) dtimer_intr_setup(void)30*4882a593Smuzhiyunvoid dtimer_intr_setup(void) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); 35*4882a593Smuzhiyun clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun #endif 38