1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * (C) Copyright 2000-2003
4*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <watchdog.h>
14*4882a593Smuzhiyun #include <command.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <asm/immap.h>
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])21*4882a593Smuzhiyun int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun rcm_t *rcm = (rcm_t *) (MMAP_RCM);
24*4882a593Smuzhiyun udelay(1000);
25*4882a593Smuzhiyun setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* we don't return! */
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
checkcpu(void)31*4882a593Smuzhiyun int checkcpu(void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun ccm_t *ccm = (ccm_t *) MMAP_CCM;
34*4882a593Smuzhiyun u16 msk;
35*4882a593Smuzhiyun u16 id = 0;
36*4882a593Smuzhiyun u8 ver;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun puts("CPU: ");
39*4882a593Smuzhiyun msk = (in_be16(&ccm->cir) >> 6);
40*4882a593Smuzhiyun ver = (in_be16(&ccm->cir) & 0x003f);
41*4882a593Smuzhiyun switch (msk) {
42*4882a593Smuzhiyun case 0x6c:
43*4882a593Smuzhiyun id = 52277;
44*4882a593Smuzhiyun break;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (id) {
48*4882a593Smuzhiyun char buf1[32], buf2[32], buf3[32];
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
51*4882a593Smuzhiyun ver);
52*4882a593Smuzhiyun printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
53*4882a593Smuzhiyun strmhz(buf1, gd->cpu_clk),
54*4882a593Smuzhiyun strmhz(buf2, gd->bus_clk),
55*4882a593Smuzhiyun strmhz(buf3, gd->arch.flb_clk));
56*4882a593Smuzhiyun printf(" INP CLK %s MHz VCO CLK %s MHz\n",
57*4882a593Smuzhiyun strmhz(buf1, gd->arch.inp_clk),
58*4882a593Smuzhiyun strmhz(buf2, gd->arch.vco_clk));
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63