1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2015 - 2016 Xilinx, Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <debug_uart.h>
10*4882a593Smuzhiyun #include <spl.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/spl.h>
14*4882a593Smuzhiyun #include <asm/arch/hardware.h>
15*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
16*4882a593Smuzhiyun
board_init_f(ulong dummy)17*4882a593Smuzhiyun void board_init_f(ulong dummy)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun board_early_init_f();
20*4882a593Smuzhiyun board_early_init_r();
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART
23*4882a593Smuzhiyun /* Uart debug for sure */
24*4882a593Smuzhiyun debug_uart_init();
25*4882a593Smuzhiyun puts("Debug uart enabled\n"); /* or printch() */
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun /* Delay is required for clocks to be propagated */
28*4882a593Smuzhiyun udelay(1000000);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Clear the BSS */
31*4882a593Smuzhiyun memset(__bss_start, 0, __bss_end - __bss_start);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* No need to call timer init - it is empty for ZynqMP */
34*4882a593Smuzhiyun board_init_r(NULL, 0);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
ps_mode_reset(ulong mode)37*4882a593Smuzhiyun static void ps_mode_reset(ulong mode)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
40*4882a593Smuzhiyun &crlapb_base->boot_pin_ctrl);
41*4882a593Smuzhiyun udelay(5);
42*4882a593Smuzhiyun writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
43*4882a593Smuzhiyun mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
44*4882a593Smuzhiyun &crlapb_base->boot_pin_ctrl);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * Set default PS_MODE1 which is used for USB ULPI phy reset
49*4882a593Smuzhiyun * Also other resets can be connected to this certain pin
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun #ifndef MODE_RESET
52*4882a593Smuzhiyun # define MODE_RESET PS_MODE1
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #ifdef CONFIG_SPL_BOARD_INIT
spl_board_init(void)56*4882a593Smuzhiyun void spl_board_init(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun preloader_console_init();
59*4882a593Smuzhiyun ps_mode_reset(MODE_RESET);
60*4882a593Smuzhiyun board_init();
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
spl_boot_device(void)64*4882a593Smuzhiyun u32 spl_boot_device(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun u32 reg = 0;
67*4882a593Smuzhiyun u8 bootmode;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
70*4882a593Smuzhiyun /* Change default boot mode at run-time */
71*4882a593Smuzhiyun writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
72*4882a593Smuzhiyun &crlapb_base->boot_mode);
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun reg = readl(&crlapb_base->boot_mode);
76*4882a593Smuzhiyun if (reg >> BOOT_MODE_ALT_SHIFT)
77*4882a593Smuzhiyun reg >>= BOOT_MODE_ALT_SHIFT;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun bootmode = reg & BOOT_MODES_MASK;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun switch (bootmode) {
82*4882a593Smuzhiyun case JTAG_MODE:
83*4882a593Smuzhiyun return BOOT_DEVICE_RAM;
84*4882a593Smuzhiyun #ifdef CONFIG_SPL_MMC_SUPPORT
85*4882a593Smuzhiyun case SD_MODE1:
86*4882a593Smuzhiyun case SD1_LSHFT_MODE: /* not working on silicon v1 */
87*4882a593Smuzhiyun /* if both controllers enabled, then these two are the second controller */
88*4882a593Smuzhiyun #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
89*4882a593Smuzhiyun return BOOT_DEVICE_MMC2;
90*4882a593Smuzhiyun /* else, fall through, the one SDHCI controller that is enabled is number 1 */
91*4882a593Smuzhiyun #endif
92*4882a593Smuzhiyun case SD_MODE:
93*4882a593Smuzhiyun case EMMC_MODE:
94*4882a593Smuzhiyun return BOOT_DEVICE_MMC1;
95*4882a593Smuzhiyun #endif
96*4882a593Smuzhiyun #ifdef CONFIG_SPL_DFU
97*4882a593Smuzhiyun case USB_MODE:
98*4882a593Smuzhiyun return BOOT_DEVICE_DFU;
99*4882a593Smuzhiyun #endif
100*4882a593Smuzhiyun #ifdef CONFIG_SPL_SATA_SUPPORT
101*4882a593Smuzhiyun case SW_SATA_MODE:
102*4882a593Smuzhiyun return BOOT_DEVICE_SATA;
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun #ifdef CONFIG_SPL_SPI_SUPPORT
105*4882a593Smuzhiyun case QSPI_MODE_24BIT:
106*4882a593Smuzhiyun case QSPI_MODE_32BIT:
107*4882a593Smuzhiyun return BOOT_DEVICE_SPI;
108*4882a593Smuzhiyun #endif
109*4882a593Smuzhiyun default:
110*4882a593Smuzhiyun printf("Invalid Boot Mode:0x%x\n", bootmode);
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)118*4882a593Smuzhiyun int spl_start_uboot(void)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun handoff_setup();
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return 0;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun #endif
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)127*4882a593Smuzhiyun int board_fit_config_name_match(const char *name)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun /* Just empty function now - can't decide what to choose */
130*4882a593Smuzhiyun debug("%s: %s\n", __func__, name);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun return 0;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun #endif
135