1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
3*4882a593Smuzhiyun * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
6*4882a593Smuzhiyun * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * (C) Copyright 2008
9*4882a593Smuzhiyun * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * (C) Copyright 2004
12*4882a593Smuzhiyun * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * (C) Copyright 2002-2004
15*4882a593Smuzhiyun * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * (C) Copyright 2003
18*4882a593Smuzhiyun * Texas Instruments <www.ti.com>
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * (C) Copyright 2002
21*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
22*4882a593Smuzhiyun * Marius Groeger <mgroeger@sysgo.de>
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * (C) Copyright 2002
25*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
26*4882a593Smuzhiyun * Alex Zuepke <azu@sysgo.de>
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <clk.h>
32*4882a593Smuzhiyun #include <common.h>
33*4882a593Smuzhiyun #include <div64.h>
34*4882a593Smuzhiyun #include <dm.h>
35*4882a593Smuzhiyun #include <asm/io.h>
36*4882a593Smuzhiyun #include <asm/arch/hardware.h>
37*4882a593Smuzhiyun #include <asm/arch/clk.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct scu_timer {
42*4882a593Smuzhiyun u32 load; /* Timer Load Register */
43*4882a593Smuzhiyun u32 counter; /* Timer Counter Register */
44*4882a593Smuzhiyun u32 control; /* Timer Control Register */
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static struct scu_timer *timer_base =
48*4882a593Smuzhiyun (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
51*4882a593Smuzhiyun #define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
52*4882a593Smuzhiyun #define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
53*4882a593Smuzhiyun #define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define TIMER_LOAD_VAL 0xFFFFFFFF
56*4882a593Smuzhiyun #define TIMER_PRESCALE 255
57*4882a593Smuzhiyun
timer_init(void)58*4882a593Smuzhiyun int timer_init(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
61*4882a593Smuzhiyun (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
62*4882a593Smuzhiyun SCUTIMER_CONTROL_ENABLE_MASK;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct udevice *dev;
65*4882a593Smuzhiyun struct clk clk;
66*4882a593Smuzhiyun int ret;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ret = uclass_get_device_by_driver(UCLASS_CLK,
69*4882a593Smuzhiyun DM_GET_DRIVER(zynq_clk), &dev);
70*4882a593Smuzhiyun if (ret)
71*4882a593Smuzhiyun return ret;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun clk.id = cpu_6or4x_clk;
74*4882a593Smuzhiyun ret = clk_request(dev, &clk);
75*4882a593Smuzhiyun if (ret < 0)
76*4882a593Smuzhiyun return ret;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun gd->cpu_clk = clk_get_rate(&clk);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun clk_free(&clk);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Load the timer counter register */
85*4882a593Smuzhiyun writel(0xFFFFFFFF, &timer_base->load);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * Start the A9Timer device
89*4882a593Smuzhiyun * Enable Auto reload mode, Clear prescaler control bits
90*4882a593Smuzhiyun * Set prescaler value, Enable the decrementer
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
93*4882a593Smuzhiyun emask);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Reset time */
96*4882a593Smuzhiyun gd->arch.lastinc = readl(&timer_base->counter) /
97*4882a593Smuzhiyun (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
98*4882a593Smuzhiyun gd->arch.tbl = 0;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun * This function is derived from PowerPC code (timebase clock frequency).
105*4882a593Smuzhiyun * On ARM it returns the number of timer ticks per second.
106*4882a593Smuzhiyun */
get_tbclk(void)107*4882a593Smuzhiyun ulong get_tbclk(void)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun return gd->arch.timer_rate_hz;
110*4882a593Smuzhiyun }
111