1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2013 Xilinx Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ZYNQ_CLK_H_ 8*4882a593Smuzhiyun #define _ZYNQ_CLK_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun enum zynq_clk { 11*4882a593Smuzhiyun armpll_clk, ddrpll_clk, iopll_clk, 12*4882a593Smuzhiyun cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, 13*4882a593Smuzhiyun ddr2x_clk, ddr3x_clk, dci_clk, 14*4882a593Smuzhiyun lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, 15*4882a593Smuzhiyun fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, 16*4882a593Smuzhiyun sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, 17*4882a593Smuzhiyun usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, 18*4882a593Smuzhiyun sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, 19*4882a593Smuzhiyun can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, 20*4882a593Smuzhiyun uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, 21*4882a593Smuzhiyun smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif 24