xref: /OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/clk.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
3*4882a593Smuzhiyun  * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun #include <clk.h>
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <asm/arch/clk.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun static const char * const clk_names[clk_max] = {
15*4882a593Smuzhiyun 	"armpll", "ddrpll", "iopll",
16*4882a593Smuzhiyun 	"cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
17*4882a593Smuzhiyun 	"ddr2x", "ddr3x", "dci",
18*4882a593Smuzhiyun 	"lqspi", "smc", "pcap", "gem0", "gem1",
19*4882a593Smuzhiyun 	"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
20*4882a593Smuzhiyun 	"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
21*4882a593Smuzhiyun 	"usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
22*4882a593Smuzhiyun 	"sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
23*4882a593Smuzhiyun 	"can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
24*4882a593Smuzhiyun 	"uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
25*4882a593Smuzhiyun 	"smc_aper", "swdt", "dbg_trc", "dbg_apb"
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /**
29*4882a593Smuzhiyun  * set_cpu_clk_info() - Setup clock information
30*4882a593Smuzhiyun  *
31*4882a593Smuzhiyun  * This function is called from common code after relocation and sets up the
32*4882a593Smuzhiyun  * clock information.
33*4882a593Smuzhiyun  */
set_cpu_clk_info(void)34*4882a593Smuzhiyun int set_cpu_clk_info(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	struct clk clk;
37*4882a593Smuzhiyun 	struct udevice *dev;
38*4882a593Smuzhiyun 	ulong rate;
39*4882a593Smuzhiyun 	int i, ret;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	ret = uclass_get_device_by_driver(UCLASS_CLK,
42*4882a593Smuzhiyun 		DM_GET_DRIVER(zynq_clk), &dev);
43*4882a593Smuzhiyun 	if (ret)
44*4882a593Smuzhiyun 		return ret;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
47*4882a593Smuzhiyun 		clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
48*4882a593Smuzhiyun 		ret = clk_request(dev, &clk);
49*4882a593Smuzhiyun 		if (ret < 0)
50*4882a593Smuzhiyun 			return ret;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 		rate = clk_get_rate(&clk) / 1000000;
53*4882a593Smuzhiyun 		if (i)
54*4882a593Smuzhiyun 			gd->bd->bi_ddr_freq = rate;
55*4882a593Smuzhiyun 		else
56*4882a593Smuzhiyun 			gd->bd->bi_arm_freq = rate;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 		clk_free(&clk);
59*4882a593Smuzhiyun 	}
60*4882a593Smuzhiyun 	gd->bd->bi_dsp_freq = 0;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /**
66*4882a593Smuzhiyun  * soc_clk_dump() - Print clock frequencies
67*4882a593Smuzhiyun  * Returns zero on success
68*4882a593Smuzhiyun  *
69*4882a593Smuzhiyun  * Implementation for the clk dump command.
70*4882a593Smuzhiyun  */
soc_clk_dump(void)71*4882a593Smuzhiyun int soc_clk_dump(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	struct udevice *dev;
74*4882a593Smuzhiyun 	int i, ret;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	ret = uclass_get_device_by_driver(UCLASS_CLK,
77*4882a593Smuzhiyun 		DM_GET_DRIVER(zynq_clk), &dev);
78*4882a593Smuzhiyun 	if (ret)
79*4882a593Smuzhiyun 		return ret;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	printf("clk\t\tfrequency\n");
82*4882a593Smuzhiyun 	for (i = 0; i < clk_max; i++) {
83*4882a593Smuzhiyun 		const char *name = clk_names[i];
84*4882a593Smuzhiyun 		if (name) {
85*4882a593Smuzhiyun 			struct clk clk;
86*4882a593Smuzhiyun 			unsigned long rate;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 			clk.id = i;
89*4882a593Smuzhiyun 			ret = clk_request(dev, &clk);
90*4882a593Smuzhiyun 			if (ret < 0)
91*4882a593Smuzhiyun 				return ret;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 			rate = clk_get_rate(&clk);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 			clk_free(&clk);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 			if (rate == (unsigned long)-ENOSYS)
98*4882a593Smuzhiyun 				printf("%10s%20s\n", name, "unknown");
99*4882a593Smuzhiyun 			else
100*4882a593Smuzhiyun 				printf("%10s%20lu\n", name, rate);
101*4882a593Smuzhiyun 		}
102*4882a593Smuzhiyun 	}
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	return 0;
105*4882a593Smuzhiyun }
106