1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2003 3*4882a593Smuzhiyun * Texas Instruments <www.ti.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (C) Copyright 2002 6*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7*4882a593Smuzhiyun * Marius Groeger <mgroeger@sysgo.de> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * (C) Copyright 2002 10*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 11*4882a593Smuzhiyun * Alex Zuepke <azu@sysgo.de> 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * (C) Copyright 2002-2004 14*4882a593Smuzhiyun * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * (C) Copyright 2004 17*4882a593Smuzhiyun * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #include <common.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define TIMER_ENABLE (1 << 7) 25*4882a593Smuzhiyun #define TIMER_MODE_MSK (1 << 6) 26*4882a593Smuzhiyun #define TIMER_MODE_FR (0 << 6) 27*4882a593Smuzhiyun #define TIMER_MODE_PD (1 << 6) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define TIMER_INT_EN (1 << 5) 30*4882a593Smuzhiyun #define TIMER_PRS_MSK (3 << 2) 31*4882a593Smuzhiyun #define TIMER_PRS_8S (1 << 3) 32*4882a593Smuzhiyun #define TIMER_SIZE_MSK (1 << 2) 33*4882a593Smuzhiyun #define TIMER_ONE_SHT (1 << 0) 34*4882a593Smuzhiyun timer_init(void)35*4882a593Smuzhiyunint timer_init (void) 36*4882a593Smuzhiyun { 37*4882a593Smuzhiyun ulong tmr_ctrl_val; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 1st disable the Timer */ 40*4882a593Smuzhiyun tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); 41*4882a593Smuzhiyun tmr_ctrl_val &= ~TIMER_ENABLE; 42*4882a593Smuzhiyun *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * The Timer Control Register has one Undefined/Shouldn't Use Bit 46*4882a593Smuzhiyun * So we should do read/modify/write Operation 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Timer Mode : Free Running 51*4882a593Smuzhiyun * Interrupt : Disabled 52*4882a593Smuzhiyun * Prescale : 8 Stage, Clk/256 53*4882a593Smuzhiyun * Tmr Siz : 16 Bit Counter 54*4882a593Smuzhiyun * Tmr in Wrapping Mode 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); 57*4882a593Smuzhiyun tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); 58*4882a593Smuzhiyun tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun return 0; 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65