1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc.
3*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <debug_uart.h>
10*4882a593Smuzhiyun #include <spl.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "init.h"
13*4882a593Smuzhiyun #include "micro-support-card.h"
14*4882a593Smuzhiyun #include "soc-info.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct uniphier_spl_initdata {
17*4882a593Smuzhiyun unsigned int soc_id;
18*4882a593Smuzhiyun void (*bcu_init)(const struct uniphier_board_data *bd);
19*4882a593Smuzhiyun void (*early_clk_init)(void);
20*4882a593Smuzhiyun int (*dpll_init)(const struct uniphier_board_data *bd);
21*4882a593Smuzhiyun int (*memconf_init)(const struct uniphier_board_data *bd);
22*4882a593Smuzhiyun void (*dram_clk_init)(void);
23*4882a593Smuzhiyun int (*umc_init)(const struct uniphier_board_data *bd);
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
27*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_LD4)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun .soc_id = UNIPHIER_LD4_ID,
30*4882a593Smuzhiyun .bcu_init = uniphier_ld4_bcu_init,
31*4882a593Smuzhiyun .early_clk_init = uniphier_ld4_early_clk_init,
32*4882a593Smuzhiyun .dpll_init = uniphier_ld4_dpll_init,
33*4882a593Smuzhiyun .memconf_init = uniphier_memconf_2ch_init,
34*4882a593Smuzhiyun .dram_clk_init = uniphier_ld4_dram_clk_init,
35*4882a593Smuzhiyun .umc_init = uniphier_ld4_umc_init,
36*4882a593Smuzhiyun },
37*4882a593Smuzhiyun #endif
38*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun .soc_id = UNIPHIER_PRO4_ID,
41*4882a593Smuzhiyun .early_clk_init = uniphier_ld4_early_clk_init,
42*4882a593Smuzhiyun .dpll_init = uniphier_pro4_dpll_init,
43*4882a593Smuzhiyun .memconf_init = uniphier_memconf_2ch_init,
44*4882a593Smuzhiyun .dram_clk_init = uniphier_ld4_dram_clk_init,
45*4882a593Smuzhiyun .umc_init = uniphier_pro4_umc_init,
46*4882a593Smuzhiyun },
47*4882a593Smuzhiyun #endif
48*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun .soc_id = UNIPHIER_SLD8_ID,
51*4882a593Smuzhiyun .bcu_init = uniphier_ld4_bcu_init,
52*4882a593Smuzhiyun .early_clk_init = uniphier_ld4_early_clk_init,
53*4882a593Smuzhiyun .dpll_init = uniphier_sld8_dpll_init,
54*4882a593Smuzhiyun .memconf_init = uniphier_memconf_2ch_init,
55*4882a593Smuzhiyun .dram_clk_init = uniphier_ld4_dram_clk_init,
56*4882a593Smuzhiyun .umc_init = uniphier_sld8_umc_init,
57*4882a593Smuzhiyun },
58*4882a593Smuzhiyun #endif
59*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun .soc_id = UNIPHIER_PRO5_ID,
62*4882a593Smuzhiyun .early_clk_init = uniphier_ld4_early_clk_init,
63*4882a593Smuzhiyun .dpll_init = uniphier_pro5_dpll_init,
64*4882a593Smuzhiyun .memconf_init = uniphier_memconf_2ch_init,
65*4882a593Smuzhiyun .dram_clk_init = uniphier_pro5_dram_clk_init,
66*4882a593Smuzhiyun .umc_init = uniphier_pro5_umc_init,
67*4882a593Smuzhiyun },
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun .soc_id = UNIPHIER_PXS2_ID,
72*4882a593Smuzhiyun .early_clk_init = uniphier_ld4_early_clk_init,
73*4882a593Smuzhiyun .dpll_init = uniphier_pxs2_dpll_init,
74*4882a593Smuzhiyun .memconf_init = uniphier_memconf_3ch_init,
75*4882a593Smuzhiyun .dram_clk_init = uniphier_pxs2_dram_clk_init,
76*4882a593Smuzhiyun .umc_init = uniphier_pxs2_umc_init,
77*4882a593Smuzhiyun },
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun .soc_id = UNIPHIER_LD6B_ID,
82*4882a593Smuzhiyun .early_clk_init = uniphier_ld4_early_clk_init,
83*4882a593Smuzhiyun .dpll_init = uniphier_pxs2_dpll_init,
84*4882a593Smuzhiyun .memconf_init = uniphier_memconf_3ch_init,
85*4882a593Smuzhiyun .dram_clk_init = uniphier_pxs2_dram_clk_init,
86*4882a593Smuzhiyun .umc_init = uniphier_pxs2_umc_init,
87*4882a593Smuzhiyun },
88*4882a593Smuzhiyun #endif
89*4882a593Smuzhiyun };
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata,uniphier_spl_initdata)90*4882a593Smuzhiyun UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun void spl_board_init(void)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun const struct uniphier_board_data *bd;
95*4882a593Smuzhiyun const struct uniphier_spl_initdata *initdata;
96*4882a593Smuzhiyun int ret;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART
99*4882a593Smuzhiyun debug_uart_init();
100*4882a593Smuzhiyun #endif
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun bd = uniphier_get_board_param();
103*4882a593Smuzhiyun if (!bd)
104*4882a593Smuzhiyun hang();
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun initdata = uniphier_get_spl_initdata();
107*4882a593Smuzhiyun if (!initdata)
108*4882a593Smuzhiyun hang();
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (initdata->bcu_init)
111*4882a593Smuzhiyun initdata->bcu_init(bd);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun initdata->early_clk_init();
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #ifdef CONFIG_SPL_SERIAL_SUPPORT
116*4882a593Smuzhiyun preloader_console_init();
117*4882a593Smuzhiyun #endif
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun ret = initdata->dpll_init(bd);
120*4882a593Smuzhiyun if (ret) {
121*4882a593Smuzhiyun pr_err("failed to init DPLL\n");
122*4882a593Smuzhiyun hang();
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun ret = initdata->memconf_init(bd);
126*4882a593Smuzhiyun if (ret) {
127*4882a593Smuzhiyun pr_err("failed to init MEMCONF\n");
128*4882a593Smuzhiyun hang();
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun initdata->dram_clk_init();
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun ret = initdata->umc_init(bd);
134*4882a593Smuzhiyun if (ret) {
135*4882a593Smuzhiyun pr_err("failed to init DRAM\n");
136*4882a593Smuzhiyun hang();
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun }
139