1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * UniPhier SC (System Control) block registers for ARMv8 SoCs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc. 5*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef SC64_REGS_H 11*4882a593Smuzhiyun #define SC64_REGS_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define SC_BASE_ADDR 0x61840000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) 16*4882a593Smuzhiyun #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) 17*4882a593Smuzhiyun #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) 18*4882a593Smuzhiyun #define SC_RSTCTRL4_ETHER (1 << 6) 19*4882a593Smuzhiyun #define SC_RSTCTRL4_NAND (1 << 0) 20*4882a593Smuzhiyun #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) 21*4882a593Smuzhiyun #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) 22*4882a593Smuzhiyun #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) 23*4882a593Smuzhiyun #define SC_RSTCTRL7_UMCSB (1 << 16) 24*4882a593Smuzhiyun #define SC_RSTCTRL7_UMCA2 (1 << 10) 25*4882a593Smuzhiyun #define SC_RSTCTRL7_UMCA1 (1 << 9) 26*4882a593Smuzhiyun #define SC_RSTCTRL7_UMCA0 (1 << 8) 27*4882a593Smuzhiyun #define SC_RSTCTRL7_UMC32 (1 << 2) 28*4882a593Smuzhiyun #define SC_RSTCTRL7_UMC31 (1 << 1) 29*4882a593Smuzhiyun #define SC_RSTCTRL7_UMC30 (1 << 0) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) 32*4882a593Smuzhiyun #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) 33*4882a593Smuzhiyun #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) 34*4882a593Smuzhiyun #define SC_CLKCTRL4_MIO (1 << 10) 35*4882a593Smuzhiyun #define SC_CLKCTRL4_STDMAC (1 << 8) 36*4882a593Smuzhiyun #define SC_CLKCTRL4_PERI (1 << 7) 37*4882a593Smuzhiyun #define SC_CLKCTRL4_ETHER (1 << 6) 38*4882a593Smuzhiyun #define SC_CLKCTRL4_NAND (1 << 0) 39*4882a593Smuzhiyun #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) 40*4882a593Smuzhiyun #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) 41*4882a593Smuzhiyun #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) 42*4882a593Smuzhiyun #define SC_CLKCTRL7_UMCSB (1 << 16) 43*4882a593Smuzhiyun #define SC_CLKCTRL7_UMC32 (1 << 2) 44*4882a593Smuzhiyun #define SC_CLKCTRL7_UMC31 (1 << 1) 45*4882a593Smuzhiyun #define SC_CLKCTRL7_UMC30 (1 << 0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) 48*4882a593Smuzhiyun #define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) 49*4882a593Smuzhiyun #define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008) 50*4882a593Smuzhiyun #define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) 51*4882a593Smuzhiyun #define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) 52*4882a593Smuzhiyun #define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) 53*4882a593Smuzhiyun #define SC_CA_GEARUPD (1 << 0) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* SC64_REGS_H */ 56