1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * UniPhier SC (System Control) block registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011-2015 Panasonic Corporation 5*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc. 6*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef ARCH_SC_REGS_H 12*4882a593Smuzhiyun #define ARCH_SC_REGS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define SC_BASE_ADDR 0x61840000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) 17*4882a593Smuzhiyun #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) 18*4882a593Smuzhiyun #define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) 21*4882a593Smuzhiyun #define SC_DPLLCTRL_SSC_EN (0x1 << 31) 22*4882a593Smuzhiyun #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) 23*4882a593Smuzhiyun #define SC_DPLLCTRL_SSC_RATE (0x1 << 15) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) 26*4882a593Smuzhiyun #define SC_DPLLCTRL2_NRSTDS (0x1 << 28) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) 29*4882a593Smuzhiyun #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) 30*4882a593Smuzhiyun #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) 35*4882a593Smuzhiyun #define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) 36*4882a593Smuzhiyun #define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) 39*4882a593Smuzhiyun #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) 40*4882a593Smuzhiyun #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) 43*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ 44*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ 45*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) 46*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) 47*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_GIO (0x1 << 6) 48*4882a593Smuzhiyun /* Pro4 or older */ 49*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) 50*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) 51*4882a593Smuzhiyun #define SC_RSTCTRL_NRST_NAND (0x1 << 2) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) 54*4882a593Smuzhiyun #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ 55*4882a593Smuzhiyun #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Pro5 or newer */ 60*4882a593Smuzhiyun #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) 61*4882a593Smuzhiyun #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */ 62*4882a593Smuzhiyun #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */ 63*4882a593Smuzhiyun #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */ 64*4882a593Smuzhiyun #define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */ 65*4882a593Smuzhiyun #define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */ 66*4882a593Smuzhiyun #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ 67*4882a593Smuzhiyun #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) 74*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ 75*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ 76*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) 77*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_MIO (0x1 << 11) 78*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) 79*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_GIO (0x1 << 6) 80*4882a593Smuzhiyun /* Pro4 or older */ 81*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_UMC (0x1 << 4) 82*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_NAND (0x1 << 2) 83*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_SBC (0x1 << 1) 84*4882a593Smuzhiyun #define SC_CLKCTRL_CEN_PERI (0x1 << 0) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Pro5 or newer */ 87*4882a593Smuzhiyun #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) 88*4882a593Smuzhiyun #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */ 89*4882a593Smuzhiyun #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */ 90*4882a593Smuzhiyun #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */ 91*4882a593Smuzhiyun #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* System reset control register */ 94*4882a593Smuzhiyun #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) 95*4882a593Smuzhiyun #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) 96*4882a593Smuzhiyun #define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif /* ARCH_SC_REGS_H */ 99