1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * UniPhier SBC (System Bus Controller) registers
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2011-2014 Panasonic Corporation
5*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef ARCH_SBC_REGS_H
11*4882a593Smuzhiyun #define ARCH_SBC_REGS_H
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SBBASE_BASE 0x58c00100
14*4882a593Smuzhiyun #define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SBBASE0 (SBBASE(0))
17*4882a593Smuzhiyun #define SBBASE1 (SBBASE(1))
18*4882a593Smuzhiyun #define SBBASE2 (SBBASE(2))
19*4882a593Smuzhiyun #define SBBASE3 (SBBASE(3))
20*4882a593Smuzhiyun #define SBBASE4 (SBBASE(4))
21*4882a593Smuzhiyun #define SBBASE5 (SBBASE(5))
22*4882a593Smuzhiyun #define SBBASE6 (SBBASE(6))
23*4882a593Smuzhiyun #define SBBASE7 (SBBASE(7))
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define SBBASE_BANK_ENABLE (0x00000001)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define SBCTRL_BASE 0x58c00200
28*4882a593Smuzhiyun #define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define SBCTRL00 SBCTRL(0, 0)
31*4882a593Smuzhiyun #define SBCTRL01 SBCTRL(0, 1)
32*4882a593Smuzhiyun #define SBCTRL02 SBCTRL(0, 2)
33*4882a593Smuzhiyun #define SBCTRL03 SBCTRL(0, 3)
34*4882a593Smuzhiyun #define SBCTRL04 (SBCTRL_BASE + 0x100)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define SBCTRL10 SBCTRL(1, 0)
37*4882a593Smuzhiyun #define SBCTRL11 SBCTRL(1, 1)
38*4882a593Smuzhiyun #define SBCTRL12 SBCTRL(1, 2)
39*4882a593Smuzhiyun #define SBCTRL13 SBCTRL(1, 3)
40*4882a593Smuzhiyun #define SBCTRL14 (SBCTRL_BASE + 0x110)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define SBCTRL20 SBCTRL(2, 0)
43*4882a593Smuzhiyun #define SBCTRL21 SBCTRL(2, 1)
44*4882a593Smuzhiyun #define SBCTRL22 SBCTRL(2, 2)
45*4882a593Smuzhiyun #define SBCTRL23 SBCTRL(2, 3)
46*4882a593Smuzhiyun #define SBCTRL24 (SBCTRL_BASE + 0x120)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define SBCTRL30 SBCTRL(3, 0)
49*4882a593Smuzhiyun #define SBCTRL31 SBCTRL(3, 1)
50*4882a593Smuzhiyun #define SBCTRL32 SBCTRL(3, 2)
51*4882a593Smuzhiyun #define SBCTRL33 SBCTRL(3, 3)
52*4882a593Smuzhiyun #define SBCTRL34 (SBCTRL_BASE + 0x130)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define SBCTRL40 SBCTRL(4, 0)
55*4882a593Smuzhiyun #define SBCTRL41 SBCTRL(4, 1)
56*4882a593Smuzhiyun #define SBCTRL42 SBCTRL(4, 2)
57*4882a593Smuzhiyun #define SBCTRL43 SBCTRL(4, 3)
58*4882a593Smuzhiyun #define SBCTRL44 (SBCTRL_BASE + 0x140)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define SBCTRL50 SBCTRL(5, 0)
61*4882a593Smuzhiyun #define SBCTRL51 SBCTRL(5, 1)
62*4882a593Smuzhiyun #define SBCTRL52 SBCTRL(5, 2)
63*4882a593Smuzhiyun #define SBCTRL53 SBCTRL(5, 3)
64*4882a593Smuzhiyun #define SBCTRL54 (SBCTRL_BASE + 0x150)
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define SBCTRL60 SBCTRL(6, 0)
67*4882a593Smuzhiyun #define SBCTRL61 SBCTRL(6, 1)
68*4882a593Smuzhiyun #define SBCTRL62 SBCTRL(6, 2)
69*4882a593Smuzhiyun #define SBCTRL63 SBCTRL(6, 3)
70*4882a593Smuzhiyun #define SBCTRL64 (SBCTRL_BASE + 0x160)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define SBCTRL70 SBCTRL(7, 0)
73*4882a593Smuzhiyun #define SBCTRL71 SBCTRL(7, 1)
74*4882a593Smuzhiyun #define SBCTRL72 SBCTRL(7, 2)
75*4882a593Smuzhiyun #define SBCTRL73 SBCTRL(7, 3)
76*4882a593Smuzhiyun #define SBCTRL74 (SBCTRL_BASE + 0x170)
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define PC0CTRL 0x598000c0
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #ifndef __ASSEMBLY__
81*4882a593Smuzhiyun #include <linux/io.h>
boot_is_swapped(void)82*4882a593Smuzhiyun static inline int boot_is_swapped(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #endif /* ARCH_SBC_REGS_H */
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