1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * UniPhier UMC (Universal Memory Controller) registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011-2014 Panasonic Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef ARCH_UMC_REGS_H 10*4882a593Smuzhiyun #define ARCH_UMC_REGS_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/bitops.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define UMC_CPURST 0x00000700 15*4882a593Smuzhiyun #define UMC_IDSRST 0x0000070C 16*4882a593Smuzhiyun #define UMC_IXMRST 0x00000714 17*4882a593Smuzhiyun #define UMC_HDMRST 0x00000718 18*4882a593Smuzhiyun #define UMC_MDMRST 0x0000071C 19*4882a593Smuzhiyun #define UMC_HDDRST 0x00000720 20*4882a593Smuzhiyun #define UMC_MDDRST 0x00000724 21*4882a593Smuzhiyun #define UMC_SIORST 0x00000728 22*4882a593Smuzhiyun #define UMC_GIORST 0x0000072C 23*4882a593Smuzhiyun #define UMC_HD2RST 0x00000734 24*4882a593Smuzhiyun #define UMC_VIORST 0x0000073C 25*4882a593Smuzhiyun #define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ 26*4882a593Smuzhiyun #define UMC_DVCRST 0x00000748 /* Pro4 */ 27*4882a593Smuzhiyun #define UMC_RGLRST 0x00000750 28*4882a593Smuzhiyun #define UMC_VPERST 0x00000758 29*4882a593Smuzhiyun #define UMC_AIORST 0x00000764 30*4882a593Smuzhiyun #define UMC_DMDRST 0x00000770 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define UMC_HDMCHSEL 0x00000898 33*4882a593Smuzhiyun #define UMC_MDMCHSEL 0x0000089C 34*4882a593Smuzhiyun #define UMC_DVCCHSEL 0x000008C8 35*4882a593Smuzhiyun #define UMC_DMDCHSEL 0x000008F0 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_FETCH 0x0000C060 38*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 39*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_COMWC0 0x0000C068 40*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_COMRC0 0x0000C06C 41*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 42*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_COMWC1 0x0000C074 43*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_COMRC1 0x0000C078 44*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_WC 0x0000C07C 45*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_RC 0x0000C080 46*4882a593Smuzhiyun #define UMC_CLKEN_SSIF_DST 0x0000C084 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define UMC_CMDCTLA 0x00000000 49*4882a593Smuzhiyun #define UMC_CMDCTLB 0x00000004 50*4882a593Smuzhiyun #define UMC_INITSET 0x00000014 51*4882a593Smuzhiyun #define UMC_INITSET_INIT1EN BIT(1) /* init without power-on wait */ 52*4882a593Smuzhiyun #define UMC_INITSET_INIT0EN BIT(0) /* init with power-on wait */ 53*4882a593Smuzhiyun #define UMC_INITSTAT 0x00000018 54*4882a593Smuzhiyun #define UMC_INITSTAT_INIT1ST BIT(1) /* init without power-on wait */ 55*4882a593Smuzhiyun #define UMC_INITSTAT_INIT0ST BIT(0) /* init with power-on wait */ 56*4882a593Smuzhiyun #define UMC_SPCCTLA 0x00000030 57*4882a593Smuzhiyun #define UMC_SPCCTLB 0x00000034 58*4882a593Smuzhiyun #define UMC_SPCSETA 0x00000038 59*4882a593Smuzhiyun #define UMC_SPCSETB 0x0000003C 60*4882a593Smuzhiyun #define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ 61*4882a593Smuzhiyun #define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ 62*4882a593Smuzhiyun #define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ 63*4882a593Smuzhiyun #define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ 64*4882a593Smuzhiyun #define UMC_SPCSETC 0x00000040 65*4882a593Smuzhiyun #define UMC_SPCSETD 0x00000044 66*4882a593Smuzhiyun #define UMC_SPCSTATA 0x00000050 67*4882a593Smuzhiyun #define UMC_SPCSTATB 0x00000054 68*4882a593Smuzhiyun #define UMC_SPCSTATC 0x00000058 69*4882a593Smuzhiyun #define UMC_ACSSETA 0x00000060 70*4882a593Smuzhiyun #define UMC_FLOWCTLA 0x00000400 71*4882a593Smuzhiyun #define UMC_FLOWCTLB 0x00000404 72*4882a593Smuzhiyun #define UMC_FLOWCTLC 0x00000408 73*4882a593Smuzhiyun #define UMC_FLOWCTLG 0x00000508 74*4882a593Smuzhiyun #define UMC_FLOWCTLOB0 0x00000520 75*4882a593Smuzhiyun #define UMC_FLOWCTLOB1 0x00000524 76*4882a593Smuzhiyun #define UMC_RDATACTL_D0 0x00000600 77*4882a593Smuzhiyun #define UMC_RDATACTL_RADLTY_SHIFT 4 78*4882a593Smuzhiyun #define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT)) 79*4882a593Smuzhiyun #define UMC_RDATACTL_RAD2LTY_SHIFT 8 80*4882a593Smuzhiyun #define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT)) 81*4882a593Smuzhiyun #define UMC_WDATACTL_D0 0x00000604 82*4882a593Smuzhiyun #define UMC_RDATACTL_D1 0x00000608 83*4882a593Smuzhiyun #define UMC_WDATACTL_D1 0x0000060C 84*4882a593Smuzhiyun #define UMC_DATASET 0x00000610 85*4882a593Smuzhiyun #define UMC_RESPCTL 0x00000624 86*4882a593Smuzhiyun #define UMC_DCCGCTL 0x00000720 87*4882a593Smuzhiyun #define UMC_DICGCTLA 0x00000724 88*4882a593Smuzhiyun #define UMC_DICGCTLB 0x00000728 89*4882a593Smuzhiyun #define UMC_ERRMASKA 0x00000958 90*4882a593Smuzhiyun #define UMC_ERRMASKB 0x0000095c 91*4882a593Smuzhiyun #define UMC_BSICMAPSET 0x00000988 92*4882a593Smuzhiyun #define UMC_DIOCTLA 0x00000C00 93*4882a593Smuzhiyun #define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ 94*4882a593Smuzhiyun #define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ 95*4882a593Smuzhiyun #define UMC_DFICUPDCTLA 0x00000C20 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* UM registers */ 98*4882a593Smuzhiyun #define UMC_MBUS0 0x00080004 99*4882a593Smuzhiyun #define UMC_MBUS1 0x00081004 100*4882a593Smuzhiyun #define UMC_MBUS2 0x00082004 101*4882a593Smuzhiyun #define UMC_MBUS3 0x00083004 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* UD registers */ 104*4882a593Smuzhiyun #define UMC_BITPERPIXELMODE_D0 0x010 105*4882a593Smuzhiyun #define UMC_PAIR1DOFF_D0 0x054 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #endif 108