1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <debug_uart.h> 9*4882a593Smuzhiyun #include <linux/io.h> 10*4882a593Smuzhiyun #include <linux/serial_reg.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "../soc-info.h" 13*4882a593Smuzhiyun #include "debug-uart.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define UNIPHIER_UART_TX 0x00 16*4882a593Smuzhiyun #define UNIPHIER_UART_LCR_MCR 0x10 17*4882a593Smuzhiyun #define UNIPHIER_UART_LSR 0x14 18*4882a593Smuzhiyun #define UNIPHIER_UART_LDR 0x24 19*4882a593Smuzhiyun _debug_uart_putc(int c)20*4882a593Smuzhiyunstatic void _debug_uart_putc(int c) 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE)) 25*4882a593Smuzhiyun ; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun writel(c, base + UNIPHIER_UART_TX); 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun _debug_uart_init(void)30*4882a593Smuzhiyunvoid _debug_uart_init(void) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; 33*4882a593Smuzhiyun unsigned int divisor; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun switch (uniphier_get_soc_id()) { 36*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_LD4) 37*4882a593Smuzhiyun case UNIPHIER_LD4_ID: 38*4882a593Smuzhiyun divisor = uniphier_ld4_debug_uart_init(); 39*4882a593Smuzhiyun break; 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_PRO4) 42*4882a593Smuzhiyun case UNIPHIER_PRO4_ID: 43*4882a593Smuzhiyun divisor = uniphier_pro4_debug_uart_init(); 44*4882a593Smuzhiyun break; 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_SLD8) 47*4882a593Smuzhiyun case UNIPHIER_SLD8_ID: 48*4882a593Smuzhiyun divisor = uniphier_sld8_debug_uart_init(); 49*4882a593Smuzhiyun break; 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_PRO5) 52*4882a593Smuzhiyun case UNIPHIER_PRO5_ID: 53*4882a593Smuzhiyun divisor = uniphier_pro5_debug_uart_init(); 54*4882a593Smuzhiyun break; 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_PXS2) 57*4882a593Smuzhiyun case UNIPHIER_PXS2_ID: 58*4882a593Smuzhiyun divisor = uniphier_pxs2_debug_uart_init(); 59*4882a593Smuzhiyun break; 60*4882a593Smuzhiyun #endif 61*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_LD6B) 62*4882a593Smuzhiyun case UNIPHIER_LD6B_ID: 63*4882a593Smuzhiyun divisor = uniphier_ld6b_debug_uart_init(); 64*4882a593Smuzhiyun break; 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) 67*4882a593Smuzhiyun case UNIPHIER_LD11_ID: 68*4882a593Smuzhiyun case UNIPHIER_LD20_ID: 69*4882a593Smuzhiyun divisor = uniphier_ld20_debug_uart_init(); 70*4882a593Smuzhiyun break; 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun default: 73*4882a593Smuzhiyun return; 74*4882a593Smuzhiyun } 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR); 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun writel(divisor, base + UNIPHIER_UART_LDR); 79*4882a593Smuzhiyun } 80*4882a593Smuzhiyun DEBUG_UART_FUNCS 81