1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2017 Socionext Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "../init.h"
10*4882a593Smuzhiyun #include "../sc64-regs.h"
11*4882a593Smuzhiyun #include "pll.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* PLL type: SSC */
14*4882a593Smuzhiyun #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
15*4882a593Smuzhiyun #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
16*4882a593Smuzhiyun #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
17*4882a593Smuzhiyun #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */
18*4882a593Smuzhiyun #define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440)
19*4882a593Smuzhiyun #define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450)
20*4882a593Smuzhiyun #define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460)
21*4882a593Smuzhiyun #define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470)
22*4882a593Smuzhiyun #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
23*4882a593Smuzhiyun #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
24*4882a593Smuzhiyun #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
25*4882a593Smuzhiyun #define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* PLL type: VPLL27 */
28*4882a593Smuzhiyun #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
29*4882a593Smuzhiyun #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* PLL type: DSPLL */
32*4882a593Smuzhiyun #define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
33*4882a593Smuzhiyun
uniphier_pxs3_pll_init(void)34*4882a593Smuzhiyun void uniphier_pxs3_pll_init(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
37*4882a593Smuzhiyun /* do nothing for SPLL */
38*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
39*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
40*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
41*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
42*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
43*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
44*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun mdelay(1);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
49*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
50*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
51*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
52*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
53*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
54*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
55*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
56*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
57*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
58*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
61*4882a593Smuzhiyun uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
64*4882a593Smuzhiyun }
65