1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2014 Panasonic Corporation 3*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/delay.h> 9*4882a593Smuzhiyun #include <linux/io.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "../init.h" 12*4882a593Smuzhiyun #include "../sc-regs.h" 13*4882a593Smuzhiyun uniphier_sld8_dpll_init(const struct uniphier_board_data * bd)14*4882a593Smuzhiyunint uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun u32 tmp; 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Set DPLL SSC parameters for DPLLCTRL3 19*4882a593Smuzhiyun * [23] DIVN_TEST 0x1 20*4882a593Smuzhiyun * [22:16] DIVN 0x50 21*4882a593Smuzhiyun * [10] FREFSEL_TEST 0x1 22*4882a593Smuzhiyun * [9:8] FREFSEL 0x2 23*4882a593Smuzhiyun * [4] ICPD_TEST 0x1 24*4882a593Smuzhiyun * [3:0] ICPD 0xb 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun tmp = readl(SC_DPLLCTRL3); 27*4882a593Smuzhiyun tmp &= ~0x00ff0717; 28*4882a593Smuzhiyun tmp |= 0x00d0061b; 29*4882a593Smuzhiyun writel(tmp, SC_DPLLCTRL3); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Set DPLL SSC parameters for DPLLCTRL 33*4882a593Smuzhiyun * <-1%> <-2%> 34*4882a593Smuzhiyun * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) 35*4882a593Smuzhiyun * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun tmp = readl(SC_DPLLCTRL); 38*4882a593Smuzhiyun tmp &= ~0x3ff07fff; 39*4882a593Smuzhiyun #ifdef DPLL_SSC_RATE_1PER 40*4882a593Smuzhiyun tmp |= 0x084018bf; 41*4882a593Smuzhiyun #else 42*4882a593Smuzhiyun tmp |= 0x084031a6; 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun writel(tmp, SC_DPLLCTRL); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * Set DPLL SSC parameters for DPLLCTRL2 48*4882a593Smuzhiyun * [31:29] SSC_STEP 0 49*4882a593Smuzhiyun * [27] SSC_REG_REF 1 50*4882a593Smuzhiyun * [26:20] SSC_M 79 (0x4f) 51*4882a593Smuzhiyun * [19:0] SSC_K 964689 (0xeb851) 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun tmp = readl(SC_DPLLCTRL2); 54*4882a593Smuzhiyun tmp &= ~0xefffffff; 55*4882a593Smuzhiyun tmp |= 0x0cfeb851; 56*4882a593Smuzhiyun writel(tmp, SC_DPLLCTRL2); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Wait 500 usec until dpll gets stable */ 59*4882a593Smuzhiyun udelay(500); 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun return 0; 62*4882a593Smuzhiyun } 63