1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2014 Panasonic Corporation 3*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <linux/errno.h> 10*4882a593Smuzhiyun #include <linux/io.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "../init.h" 13*4882a593Smuzhiyun #include "../sc-regs.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #undef DPLL_SSC_RATE_1PER 16*4882a593Smuzhiyun uniphier_pro4_dpll_init(const struct uniphier_board_data * bd)17*4882a593Smuzhiyunint uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun unsigned int dram_freq = bd->dram_freq; 20*4882a593Smuzhiyun u32 tmp; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Set Frequency 24*4882a593Smuzhiyun * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) 25*4882a593Smuzhiyun * to FOUT ( DPLLCTRL.bit[29:20] ) 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun tmp = readl(SC_DPLLCTRL); 28*4882a593Smuzhiyun tmp &= ~(0x000f0000); 29*4882a593Smuzhiyun switch (dram_freq) { 30*4882a593Smuzhiyun case 1333: 31*4882a593Smuzhiyun tmp |= 0x000d0000; 32*4882a593Smuzhiyun break; 33*4882a593Smuzhiyun case 1600: 34*4882a593Smuzhiyun tmp |= 0x000c0000; 35*4882a593Smuzhiyun break; 36*4882a593Smuzhiyun default: 37*4882a593Smuzhiyun pr_err("Unsupported frequency"); 38*4882a593Smuzhiyun return -EINVAL; 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Set Moduration rate 43*4882a593Smuzhiyun * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #if defined(DPLL_SSC_RATE_1PER) 46*4882a593Smuzhiyun tmp &= ~0x00008000; 47*4882a593Smuzhiyun #else 48*4882a593Smuzhiyun tmp |= 0x00008000; 49*4882a593Smuzhiyun #endif 50*4882a593Smuzhiyun writel(tmp, SC_DPLLCTRL); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun tmp = readl(SC_DPLLCTRL2); 53*4882a593Smuzhiyun tmp |= SC_DPLLCTRL2_NRSTDS; 54*4882a593Smuzhiyun writel(tmp, SC_DPLLCTRL2); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Wait until dpll gets stable */ 57*4882a593Smuzhiyun udelay(500); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun return 0; 60*4882a593Smuzhiyun } 61