1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <spl.h>
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "../init.h"
13*4882a593Smuzhiyun #include "../sc64-regs.h"
14*4882a593Smuzhiyun #include "../sg-regs.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SDCTRL_EMMC_HW_RESET 0x59810280
17*4882a593Smuzhiyun
uniphier_ld11_clk_init(void)18*4882a593Smuzhiyun void uniphier_ld11_clk_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun /* if booted from a device other than USB, without stand-by MPU */
21*4882a593Smuzhiyun if ((readl(SG_PINMON0) & BIT(27)) &&
22*4882a593Smuzhiyun uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
23*4882a593Smuzhiyun writel(1, SG_ETPHYPSHUT);
24*4882a593Smuzhiyun writel(1, SG_ETPHYCNT);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun udelay(1); /* wait for regulator level 1.1V -> 2.5V */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun writel(3, SG_ETPHYCNT);
29*4882a593Smuzhiyun writel(3, SG_ETPHYPSHUT);
30*4882a593Smuzhiyun writel(7, SG_ETPHYCNT);
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* TODO: use "mmc-pwrseq-emmc" */
34*4882a593Smuzhiyun writel(1, SDCTRL_EMMC_HW_RESET);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #ifdef CONFIG_USB_EHCI_HCD
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun /* FIXME: the current clk driver can not handle parents */
39*4882a593Smuzhiyun u32 tmp;
40*4882a593Smuzhiyun int ch;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun tmp = readl(SC_CLKCTRL4);
43*4882a593Smuzhiyun tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
44*4882a593Smuzhiyun writel(tmp, SC_CLKCTRL4);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun for (ch = 0; ch < 3; ch++) {
47*4882a593Smuzhiyun void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun writel(0x82280600, phyctrl + 8 * ch);
50*4882a593Smuzhiyun writel(0x00000106, phyctrl + 8 * ch + 4);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun }
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