xref: /OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/clk/clk-early-ld4.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2011-2014 Panasonic Corporation
3*4882a593Smuzhiyun  * Copyright (C) 2015-2017 Socionext Inc.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <spl.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include "../init.h"
13*4882a593Smuzhiyun #include "../sc-regs.h"
14*4882a593Smuzhiyun 
uniphier_ld4_early_clk_init(void)15*4882a593Smuzhiyun void uniphier_ld4_early_clk_init(void)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	u32 tmp;
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun 	/* deassert reset */
20*4882a593Smuzhiyun 	if (spl_boot_device() != BOOT_DEVICE_NAND) {
21*4882a593Smuzhiyun 		tmp = readl(SC_RSTCTRL);
22*4882a593Smuzhiyun 		tmp &= ~SC_RSTCTRL_NRST_NAND;
23*4882a593Smuzhiyun 		writel(tmp, SC_RSTCTRL);
24*4882a593Smuzhiyun 	};
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	/* provide clocks */
27*4882a593Smuzhiyun 	tmp = readl(SC_CLKCTRL);
28*4882a593Smuzhiyun 	tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
29*4882a593Smuzhiyun 	writel(tmp, SC_CLKCTRL);
30*4882a593Smuzhiyun 	readl(SC_CLKCTRL); /* dummy read */
31*4882a593Smuzhiyun }
32