xref: /OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/clk/clk-dram-pro5.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2015-2017 Socionext Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include "../init.h"
10*4882a593Smuzhiyun #include "../sc-regs.h"
11*4882a593Smuzhiyun 
uniphier_pro5_dram_clk_init(void)12*4882a593Smuzhiyun void uniphier_pro5_dram_clk_init(void)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun 	u32 tmp;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun 	/*
17*4882a593Smuzhiyun 	 * deassert reset
18*4882a593Smuzhiyun 	 * UMCA2: Ch1 (DDR3)
19*4882a593Smuzhiyun 	 * UMCA1, UMC31: Ch0 (WIO1)
20*4882a593Smuzhiyun 	 * UMCA0, UMC30: Ch0 (WIO0)
21*4882a593Smuzhiyun 	 */
22*4882a593Smuzhiyun 	tmp = readl(SC_RSTCTRL4);
23*4882a593Smuzhiyun 	tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
24*4882a593Smuzhiyun 	       SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
25*4882a593Smuzhiyun 	       SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
26*4882a593Smuzhiyun 	writel(tmp, SC_RSTCTRL4);
27*4882a593Smuzhiyun 	readl(SC_RSTCTRL4); /* dummy read */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun 	/* provide clocks */
30*4882a593Smuzhiyun 	tmp = readl(SC_CLKCTRL4);
31*4882a593Smuzhiyun 	tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
32*4882a593Smuzhiyun 	       SC_CLKCTRL4_CEN_UMC0;
33*4882a593Smuzhiyun 	writel(tmp, SC_CLKCTRL4);
34*4882a593Smuzhiyun 	readl(SC_CLKCTRL4); /* dummy read */
35*4882a593Smuzhiyun }
36