1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2012-2015 Panasonic Corporation 3*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc. 4*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <config.h> 10*4882a593Smuzhiyun#include <linux/linkage.h> 11*4882a593Smuzhiyun#include <linux/sizes.h> 12*4882a593Smuzhiyun#include <asm/system.h> 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunENTRY(lowlevel_init) 15*4882a593Smuzhiyun mov r8, lr @ persevere link reg across call 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * The UniPhier Boot ROM loads SPL code to the L2 cache. 19*4882a593Smuzhiyun * But CPUs can only do instruction fetch now because start.S has 20*4882a593Smuzhiyun * cleared C and M bits. 21*4882a593Smuzhiyun * First we need to turn on MMU and Dcache again to get back 22*4882a593Smuzhiyun * data access to L2. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 25*4882a593Smuzhiyun orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache 26*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun#ifdef CONFIG_DEBUG_LL 29*4882a593Smuzhiyun bl debug_ll_init 30*4882a593Smuzhiyun#endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun bl setup_init_ram @ RAM area for stack and page table 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * Now we are using the page table embedded in the Boot ROM. 36*4882a593Smuzhiyun * What we need to do next is to create a page table and switch 37*4882a593Smuzhiyun * over to it. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun bl create_page_table 40*4882a593Smuzhiyun bl __v7_flush_dcache_all 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Disable MMU and Dcache before switching Page Table */ 43*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 44*4882a593Smuzhiyun bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache 45*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun bl enable_mmu 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun mov lr, r8 @ restore link 50*4882a593Smuzhiyun mov pc, lr @ back to my caller 51*4882a593SmuzhiyunENDPROC(lowlevel_init) 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunENTRY(enable_mmu) 54*4882a593Smuzhiyun mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register) 55*4882a593Smuzhiyun bic r0, r0, #0x37 56*4882a593Smuzhiyun orr r0, r0, #0x20 @ disable TTBR1 57*4882a593Smuzhiyun mcr p15, 0, r0, c2, c0, 2 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA 60*4882a593Smuzhiyun mcr p15, 0, r0, c2, c0, 0 @ TTBR0 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun mov r0, #0 63*4882a593Smuzhiyun mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun mov r0, #-1 @ manager for all domains (No permission check) 66*4882a593Smuzhiyun mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun dsb 69*4882a593Smuzhiyun isb 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * MMU on: 72*4882a593Smuzhiyun * TLBs was already invalidated in "../start.S" 73*4882a593Smuzhiyun * So, we don't need to invalidate it here. 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 76*4882a593Smuzhiyun orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable 77*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun mov pc, lr 80*4882a593SmuzhiyunENDPROC(enable_mmu) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun/* 83*4882a593Smuzhiyun * For PH1-Pro4 or older SoCs, the size of WAY is 32KB. 84*4882a593Smuzhiyun * It is large enough for tmp RAM. 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun#define BOOT_RAM_SIZE (SZ_32K) 87*4882a593Smuzhiyun#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE)) 88*4882a593Smuzhiyun#define BOOT_RAM_WAYS (0x00000100) @ way 8 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun#define SSCO_BASE 0x506c0000 91*4882a593Smuzhiyun#define SSCOPE 0x244 92*4882a593Smuzhiyun#define SSCOQM 0x248 93*4882a593Smuzhiyun#define SSCOQAD 0x24c 94*4882a593Smuzhiyun#define SSCOQSZ 0x250 95*4882a593Smuzhiyun#define SSCOQWN 0x258 96*4882a593Smuzhiyun#define SSCOPPQSEF 0x25c 97*4882a593Smuzhiyun#define SSCOLPQS 0x260 98*4882a593Smuzhiyun 99*4882a593SmuzhiyunENTRY(setup_init_ram) 100*4882a593Smuzhiyun ldr r1, = SSCO_BASE 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Touch to zero for the boot way */ 103*4882a593Smuzhiyun0: ldr r0, = 0x00408006 @ touch to zero with address range 104*4882a593Smuzhiyun str r0, [r1, #SSCOQM] 105*4882a593Smuzhiyun ldr r0, = BOOT_RAM_BASE 106*4882a593Smuzhiyun str r0, [r1, #SSCOQAD] 107*4882a593Smuzhiyun ldr r0, = BOOT_RAM_SIZE 108*4882a593Smuzhiyun str r0, [r1, #SSCOQSZ] 109*4882a593Smuzhiyun ldr r0, = BOOT_RAM_WAYS 110*4882a593Smuzhiyun str r0, [r1, #SSCOQWN] 111*4882a593Smuzhiyun ldr r0, [r1, #SSCOPPQSEF] 112*4882a593Smuzhiyun cmp r0, #0 @ check if the command is successfully set 113*4882a593Smuzhiyun bne 0b @ try again if an error occurs 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun1: ldr r0, [r1, #SSCOLPQS] 116*4882a593Smuzhiyun cmp r0, #0x4 117*4882a593Smuzhiyun bne 1b @ wait until the operation is completed 118*4882a593Smuzhiyun str r0, [r1, #SSCOLPQS] @ clear the complete notification flag 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun mov pc, lr 121*4882a593SmuzhiyunENDPROC(setup_init_ram) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun#define DEVICE 0x00002002 /* Non-shareable Device */ 124*4882a593Smuzhiyun#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ 125*4882a593Smuzhiyun 126*4882a593SmuzhiyunENTRY(create_page_table) 127*4882a593Smuzhiyun ldr r0, = DEVICE 128*4882a593Smuzhiyun ldr r1, = BOOT_RAM_BASE 129*4882a593Smuzhiyun mov r12, r1 @ r12 is preserved during D-cache flush 130*4882a593Smuzhiyun0: str r0, [r1], #4 @ specify all the sections as Device 131*4882a593Smuzhiyun adds r0, r0, #0x00100000 132*4882a593Smuzhiyun bcc 0b 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun ldr r0, = NORMAL 135*4882a593Smuzhiyun str r0, [r12] @ mark the first section as Normal 136*4882a593Smuzhiyun add r0, r0, #0x00100000 137*4882a593Smuzhiyun str r0, [r12, #4] @ mark the second section as Normal 138*4882a593Smuzhiyun mov pc, lr 139*4882a593SmuzhiyunENDPROC(create_page_table) 140