1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * On-chip UART initializaion for low-level debugging 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <linux/serial_reg.h> 10*4882a593Smuzhiyun#include <linux/linkage.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include "../bcu/bcu-regs.h" 13*4882a593Smuzhiyun#include "../sc-regs.h" 14*4882a593Smuzhiyun#include "../sg-regs.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#if !defined(CONFIG_DEBUG_SEMIHOSTING) 17*4882a593Smuzhiyun#include CONFIG_DEBUG_LL_INCLUDE 18*4882a593Smuzhiyun#endif 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun#define BAUDRATE 115200 21*4882a593Smuzhiyun#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d)) 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunENTRY(debug_ll_init) 24*4882a593Smuzhiyun ldr r0, =SG_REVISION 25*4882a593Smuzhiyun ldr r1, [r0] 26*4882a593Smuzhiyun and r1, r1, #SG_REVISION_TYPE_MASK 27*4882a593Smuzhiyun mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun#if defined(CONFIG_ARCH_UNIPHIER_LD4) 30*4882a593Smuzhiyun#define UNIPHIER_LD4_UART_CLK 36864000 31*4882a593Smuzhiyun cmp r1, #0x26 32*4882a593Smuzhiyun bne ld4_end 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun ldr r0, =SG_IECTRL 35*4882a593Smuzhiyun ldr r1, [r0] 36*4882a593Smuzhiyun orr r1, r1, #1 37*4882a593Smuzhiyun str r1, [r0] 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun b init_uart 44*4882a593Smuzhiyunld4_end: 45*4882a593Smuzhiyun#endif 46*4882a593Smuzhiyun#if defined(CONFIG_ARCH_UNIPHIER_PRO4) 47*4882a593Smuzhiyun#define UNIPHIER_PRO4_UART_CLK 73728000 48*4882a593Smuzhiyun cmp r1, #0x28 49*4882a593Smuzhiyun bne pro4_end 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun ldr r0, =SG_LOADPINCTRL 54*4882a593Smuzhiyun mov r1, #1 55*4882a593Smuzhiyun str r1, [r0] 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ldr r0, =SC_CLKCTRL 58*4882a593Smuzhiyun ldr r1, [r0] 59*4882a593Smuzhiyun orr r1, r1, #SC_CLKCTRL_CEN_PERI 60*4882a593Smuzhiyun str r1, [r0] 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun b init_uart 65*4882a593Smuzhiyunpro4_end: 66*4882a593Smuzhiyun#endif 67*4882a593Smuzhiyun#if defined(CONFIG_ARCH_UNIPHIER_SLD8) 68*4882a593Smuzhiyun#define UNIPHIER_SLD8_UART_CLK 80000000 69*4882a593Smuzhiyun cmp r1, #0x29 70*4882a593Smuzhiyun bne sld8_end 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun ldr r0, =SG_IECTRL 73*4882a593Smuzhiyun ldr r1, [r0] 74*4882a593Smuzhiyun orr r1, r1, #1 75*4882a593Smuzhiyun str r1, [r0] 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun b init_uart 82*4882a593Smuzhiyunsld8_end: 83*4882a593Smuzhiyun#endif 84*4882a593Smuzhiyun#if defined(CONFIG_ARCH_UNIPHIER_PRO5) 85*4882a593Smuzhiyun#define UNIPHIER_PRO5_UART_CLK 73728000 86*4882a593Smuzhiyun cmp r1, #0x2A 87*4882a593Smuzhiyun bne pro5_end 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0 90*4882a593Smuzhiyun sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1 91*4882a593Smuzhiyun sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2 92*4882a593Smuzhiyun sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun ldr r0, =SG_LOADPINCTRL 95*4882a593Smuzhiyun mov r1, #1 96*4882a593Smuzhiyun str r1, [r0] 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun ldr r0, =SC_CLKCTRL 99*4882a593Smuzhiyun ldr r1, [r0] 100*4882a593Smuzhiyun orr r1, r1, #SC_CLKCTRL_CEN_PERI 101*4882a593Smuzhiyun str r1, [r0] 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun b init_uart 106*4882a593Smuzhiyunpro5_end: 107*4882a593Smuzhiyun#endif 108*4882a593Smuzhiyun#if defined(CONFIG_ARCH_UNIPHIER_PXS2) 109*4882a593Smuzhiyun#define UNIPHIER_PXS2_UART_CLK 88900000 110*4882a593Smuzhiyun cmp r1, #0x2E 111*4882a593Smuzhiyun bne pxs2_end 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun ldr r0, =SG_IECTRL 114*4882a593Smuzhiyun ldr r1, [r0] 115*4882a593Smuzhiyun orr r1, r1, #1 116*4882a593Smuzhiyun str r1, [r0] 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0 119*4882a593Smuzhiyun sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1 120*4882a593Smuzhiyun sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2 121*4882a593Smuzhiyun sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun ldr r0, =SC_CLKCTRL 124*4882a593Smuzhiyun ldr r1, [r0] 125*4882a593Smuzhiyun orr r1, r1, #SC_CLKCTRL_CEN_PERI 126*4882a593Smuzhiyun str r1, [r0] 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun b init_uart 131*4882a593Smuzhiyunpxs2_end: 132*4882a593Smuzhiyun#endif 133*4882a593Smuzhiyun#if defined(CONFIG_ARCH_UNIPHIER_LD6B) 134*4882a593Smuzhiyun#define UNIPHIER_LD6B_UART_CLK 88900000 135*4882a593Smuzhiyun cmp r1, #0x2F 136*4882a593Smuzhiyun bne ld6b_end 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun ldr r0, =SG_IECTRL 139*4882a593Smuzhiyun ldr r1, [r0] 140*4882a593Smuzhiyun orr r1, r1, #1 141*4882a593Smuzhiyun str r1, [r0] 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0 144*4882a593Smuzhiyun sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1 145*4882a593Smuzhiyun sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun ldr r0, =SC_CLKCTRL 148*4882a593Smuzhiyun ldr r1, [r0] 149*4882a593Smuzhiyun orr r1, r1, #SC_CLKCTRL_CEN_PERI 150*4882a593Smuzhiyun str r1, [r0] 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun b init_uart 155*4882a593Smuzhiyunld6b_end: 156*4882a593Smuzhiyun#endif 157*4882a593Smuzhiyun mov pc, lr 158*4882a593Smuzhiyun 159*4882a593Smuzhiyuninit_uart: 160*4882a593Smuzhiyun addruart r0, r1, r2 161*4882a593Smuzhiyun mov r1, #UART_LCR_WLEN8 << 8 162*4882a593Smuzhiyun str r1, [r0, #0x10] 163*4882a593Smuzhiyun str r3, [r0, #0x24] 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun mov pc, lr 166*4882a593SmuzhiyunENDPROC(debug_ll_init) 167