1*4882a593Smuzhiyunif ARCH_UNIPHIER 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig SYS_CONFIG_NAME 4*4882a593Smuzhiyun default "uniphier" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunconfig ARCH_UNIPHIER_32BIT 7*4882a593Smuzhiyun bool 8*4882a593Smuzhiyun select CPU_V7 9*4882a593Smuzhiyun select CPU_V7_HAS_NONSEC 10*4882a593Smuzhiyun select ARMV7_NONSEC 11*4882a593Smuzhiyun select ARCH_SUPPORT_PSCI 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunchoice 14*4882a593Smuzhiyun prompt "UniPhier SoC select" 15*4882a593Smuzhiyun default ARCH_UNIPHIER_PRO4 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunconfig ARCH_UNIPHIER_LD4_SLD8 18*4882a593Smuzhiyun bool "UniPhier LD4/sLD8 SoCs" 19*4882a593Smuzhiyun select ARCH_UNIPHIER_32BIT 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunconfig ARCH_UNIPHIER_PRO4 22*4882a593Smuzhiyun bool "UniPhier Pro4 SoC" 23*4882a593Smuzhiyun select ARCH_UNIPHIER_32BIT 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunconfig ARCH_UNIPHIER_PRO5_PXS2_LD6B 26*4882a593Smuzhiyun bool "UniPhier Pro5/PXs2/LD6b SoCs" 27*4882a593Smuzhiyun select ARCH_UNIPHIER_32BIT 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunconfig ARCH_UNIPHIER_V8_MULTI 30*4882a593Smuzhiyun bool "UniPhier V8 SoCs" 31*4882a593Smuzhiyun depends on !SPL 32*4882a593Smuzhiyun select ARM64 33*4882a593Smuzhiyun select CMD_UNZIP 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunendchoice 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunconfig ARCH_UNIPHIER_LD4 38*4882a593Smuzhiyun bool "Enable UniPhier LD4 SoC support" 39*4882a593Smuzhiyun depends on ARCH_UNIPHIER_LD4_SLD8 40*4882a593Smuzhiyun default y 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunconfig ARCH_UNIPHIER_SLD8 43*4882a593Smuzhiyun bool "Enable UniPhier sLD8 SoC support" 44*4882a593Smuzhiyun depends on ARCH_UNIPHIER_LD4_SLD8 45*4882a593Smuzhiyun default y 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunconfig ARCH_UNIPHIER_PRO5 48*4882a593Smuzhiyun bool "Enable UniPhier Pro5 SoC support" 49*4882a593Smuzhiyun depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B 50*4882a593Smuzhiyun default y 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunconfig ARCH_UNIPHIER_PXS2 53*4882a593Smuzhiyun bool "Enable UniPhier Pxs2 SoC support" 54*4882a593Smuzhiyun depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B 55*4882a593Smuzhiyun default y 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunconfig ARCH_UNIPHIER_LD6B 58*4882a593Smuzhiyun bool "Enable UniPhier LD6b SoC support" 59*4882a593Smuzhiyun depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B 60*4882a593Smuzhiyun default y 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunconfig ARCH_UNIPHIER_LD11 63*4882a593Smuzhiyun bool "Enable UniPhier LD11 SoC support" 64*4882a593Smuzhiyun depends on ARCH_UNIPHIER_V8_MULTI 65*4882a593Smuzhiyun default y 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunconfig ARCH_UNIPHIER_LD20 68*4882a593Smuzhiyun bool "Enable UniPhier LD20 SoC support" 69*4882a593Smuzhiyun depends on ARCH_UNIPHIER_V8_MULTI 70*4882a593Smuzhiyun select OF_BOARD_SETUP 71*4882a593Smuzhiyun default y 72*4882a593Smuzhiyun 73*4882a593Smuzhiyunconfig ARCH_UNIPHIER_PXS3 74*4882a593Smuzhiyun bool "Enable UniPhier PXs3 SoC support" 75*4882a593Smuzhiyun depends on ARCH_UNIPHIER_V8_MULTI 76*4882a593Smuzhiyun default y 77*4882a593Smuzhiyun 78*4882a593Smuzhiyunconfig CACHE_UNIPHIER 79*4882a593Smuzhiyun bool "Enable the UniPhier L2 cache controller" 80*4882a593Smuzhiyun depends on ARCH_UNIPHIER_32BIT 81*4882a593Smuzhiyun select SYS_CACHE_SHIFT_7 82*4882a593Smuzhiyun default y 83*4882a593Smuzhiyun help 84*4882a593Smuzhiyun This option allows to use the UniPhier System Cache as L2 cache. 85*4882a593Smuzhiyun 86*4882a593Smuzhiyunconfig MICRO_SUPPORT_CARD 87*4882a593Smuzhiyun bool "Use Micro Support Card" 88*4882a593Smuzhiyun help 89*4882a593Smuzhiyun This option provides support for the expansion board, available 90*4882a593Smuzhiyun on some UniPhier reference boards. 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun Say Y to use the on-board UART, Ether, LED devices. 93*4882a593Smuzhiyun 94*4882a593Smuzhiyunconfig CMD_PINMON 95*4882a593Smuzhiyun bool "Enable boot mode pins monitor command" 96*4882a593Smuzhiyun default y 97*4882a593Smuzhiyun help 98*4882a593Smuzhiyun The command "pinmon" shows the state of the boot mode pins. 99*4882a593Smuzhiyun The boot mode pins are latched when the system reset is deasserted 100*4882a593Smuzhiyun and determine which device the system should load a boot image from. 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunconfig CMD_DDRPHY_DUMP 103*4882a593Smuzhiyun bool "Enable dump command of DDR PHY parameters" 104*4882a593Smuzhiyun depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || \ 105*4882a593Smuzhiyun ARCH_UNIPHIER_SLD8 || ARCH_UNIPHIER_LD11 106*4882a593Smuzhiyun default y 107*4882a593Smuzhiyun help 108*4882a593Smuzhiyun The command "ddrphy" shows the resulting parameters of DDR PHY 109*4882a593Smuzhiyun training; it is useful for the evaluation of DDR PHY training. 110*4882a593Smuzhiyun 111*4882a593Smuzhiyunconfig CMD_DDRMPHY_DUMP 112*4882a593Smuzhiyun bool "Enable dump command of DDR Multi PHY parameters" 113*4882a593Smuzhiyun depends on ARCH_UNIPHIER_PXS2 || ARCH_UNIPHIER_LD6B 114*4882a593Smuzhiyun default y 115*4882a593Smuzhiyun help 116*4882a593Smuzhiyun The command "ddrmphy" shows the resulting parameters of DDR Multi PHY 117*4882a593Smuzhiyun training; it is useful for the evaluation of DDR Multi PHY training. 118*4882a593Smuzhiyun 119*4882a593Smuzhiyunendif 120