1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <errno.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/arch-tegra/xusb-padctl.h> 11*4882a593Smuzhiyun tegra_xusb_phy_get(unsigned int type)12*4882a593Smuzhiyunstruct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type) 13*4882a593Smuzhiyun { 14*4882a593Smuzhiyun return NULL; 15*4882a593Smuzhiyun } 16*4882a593Smuzhiyun tegra_xusb_phy_prepare(struct tegra_xusb_phy * phy)17*4882a593Smuzhiyunint __weak tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun return -ENOSYS; 20*4882a593Smuzhiyun } 21*4882a593Smuzhiyun tegra_xusb_phy_enable(struct tegra_xusb_phy * phy)22*4882a593Smuzhiyunint __weak tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun return -ENOSYS; 25*4882a593Smuzhiyun } 26*4882a593Smuzhiyun tegra_xusb_phy_disable(struct tegra_xusb_phy * phy)27*4882a593Smuzhiyunint __weak tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun return -ENOSYS; 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun tegra_xusb_phy_unprepare(struct tegra_xusb_phy * phy)32*4882a593Smuzhiyunint __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun return -ENOSYS; 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun tegra_xusb_padctl_init(void)37*4882a593Smuzhiyunvoid __weak tegra_xusb_padctl_init(void) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun } 40