1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
8*4882a593Smuzhiyun #define _TEGRA_XUSB_PADCTL_COMMON_H_
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <fdtdec.h>
12*4882a593Smuzhiyun #include <dm/ofnode.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <asm/arch-tegra/xusb-padctl.h>
16*4882a593Smuzhiyun #include <linux/ioport.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct tegra_xusb_padctl_lane {
19*4882a593Smuzhiyun const char *name;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun unsigned int offset;
22*4882a593Smuzhiyun unsigned int shift;
23*4882a593Smuzhiyun unsigned int mask;
24*4882a593Smuzhiyun unsigned int iddq;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun const unsigned int *funcs;
27*4882a593Smuzhiyun unsigned int num_funcs;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct tegra_xusb_phy_ops {
31*4882a593Smuzhiyun int (*prepare)(struct tegra_xusb_phy *phy);
32*4882a593Smuzhiyun int (*enable)(struct tegra_xusb_phy *phy);
33*4882a593Smuzhiyun int (*disable)(struct tegra_xusb_phy *phy);
34*4882a593Smuzhiyun int (*unprepare)(struct tegra_xusb_phy *phy);
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun struct tegra_xusb_phy {
38*4882a593Smuzhiyun unsigned int type;
39*4882a593Smuzhiyun const struct tegra_xusb_phy_ops *ops;
40*4882a593Smuzhiyun struct tegra_xusb_padctl *padctl;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct tegra_xusb_padctl_pin {
44*4882a593Smuzhiyun const struct tegra_xusb_padctl_lane *lane;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun unsigned int func;
47*4882a593Smuzhiyun int iddq;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define MAX_GROUPS 5
51*4882a593Smuzhiyun #define MAX_PINS 7
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct tegra_xusb_padctl_group {
54*4882a593Smuzhiyun const char *name;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun const char *pins[MAX_PINS];
57*4882a593Smuzhiyun unsigned int num_pins;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun const char *func;
60*4882a593Smuzhiyun int iddq;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct tegra_xusb_padctl_soc {
64*4882a593Smuzhiyun const struct tegra_xusb_padctl_lane *lanes;
65*4882a593Smuzhiyun unsigned int num_lanes;
66*4882a593Smuzhiyun const char *const *functions;
67*4882a593Smuzhiyun unsigned int num_functions;
68*4882a593Smuzhiyun struct tegra_xusb_phy *phys;
69*4882a593Smuzhiyun unsigned int num_phys;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct tegra_xusb_padctl_config {
73*4882a593Smuzhiyun const char *name;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun struct tegra_xusb_padctl_group groups[MAX_GROUPS];
76*4882a593Smuzhiyun unsigned int num_groups;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun struct tegra_xusb_padctl {
80*4882a593Smuzhiyun const struct tegra_xusb_padctl_soc *socdata;
81*4882a593Smuzhiyun struct tegra_xusb_padctl_config config;
82*4882a593Smuzhiyun struct resource regs;
83*4882a593Smuzhiyun unsigned int enable;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun extern struct tegra_xusb_padctl padctl;
87*4882a593Smuzhiyun
padctl_readl(struct tegra_xusb_padctl * padctl,unsigned long offset)88*4882a593Smuzhiyun static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
89*4882a593Smuzhiyun unsigned long offset)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return readl(padctl->regs.start + offset);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
padctl_writel(struct tegra_xusb_padctl * padctl,u32 value,unsigned long offset)94*4882a593Smuzhiyun static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
95*4882a593Smuzhiyun u32 value, unsigned long offset)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun writel(value, padctl->regs.start + offset);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
101*4882a593Smuzhiyun const struct tegra_xusb_padctl_soc *socdata);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #endif
104