1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010, 2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _WARMBOOT_AVP_H_ 9*4882a593Smuzhiyun #define _WARMBOOT_AVP_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define TEGRA_DEV_L 0 12*4882a593Smuzhiyun #define TEGRA_DEV_H 1 13*4882a593Smuzhiyun #define TEGRA_DEV_U 2 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 16*4882a593Smuzhiyun #define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) 19*4882a593Smuzhiyun #define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define USEC_CFG_DIVISOR_MASK 0xffff 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CONFIG_CTL_TBE (1 << 7) 24*4882a593Smuzhiyun #define CONFIG_CTL_JTAG (1 << 6) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CPU_RST (1 << 0) 27*4882a593Smuzhiyun #define CLK_ENB_CPU (1 << 0) 28*4882a593Smuzhiyun #define SWR_TRIG_SYS_RST (1 << 2) 29*4882a593Smuzhiyun #define SWR_CSITE_RST (1 << 9) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PWRGATE_STATUS_CPU (1 << 0) 32*4882a593Smuzhiyun #define PWRGATE_TOGGLE_PARTID_CPU (0 << 0) 33*4882a593Smuzhiyun #define PWRGATE_TOGGLE_START (1 << 8) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0) 36*4882a593Smuzhiyun #define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8) 37*4882a593Smuzhiyun #define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8) 38*4882a593Smuzhiyun #define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9) 39*4882a593Smuzhiyun #define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CPU_CMPLX_CPURESET0 (1 << 0) 42*4882a593Smuzhiyun #define CPU_CMPLX_CPURESET1 (1 << 1) 43*4882a593Smuzhiyun #define CPU_CMPLX_DERESET0 (1 << 4) 44*4882a593Smuzhiyun #define CPU_CMPLX_DERESET1 (1 << 5) 45*4882a593Smuzhiyun #define CPU_CMPLX_DBGRESET0 (1 << 12) 46*4882a593Smuzhiyun #define CPU_CMPLX_DBGRESET1 (1 << 13) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) 49*4882a593Smuzhiyun #define PLLM_OUT1_CLKEN_ENABLE (1 << 1) 50*4882a593Smuzhiyun #define PLLM_OUT1_RATIO_VAL_8 (8 << 8) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define SCLK_SYS_STATE_IDLE (1 << 28) 53*4882a593Smuzhiyun #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) 54*4882a593Smuzhiyun #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) 55*4882a593Smuzhiyun #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) 56*4882a593Smuzhiyun #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define EVENT_ZERO_VAL_20 (20 << 0) 59*4882a593Smuzhiyun #define EVENT_MSEC (1 << 24) 60*4882a593Smuzhiyun #define EVENT_JTAG (1 << 28) 61*4882a593Smuzhiyun #define EVENT_MODE_STOP (2 << 29) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define CCLK_PLLP_BURST_POLICY 0x20004444 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif 66