1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors.
3*4882a593Smuzhiyun * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <tps6586x.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/tegra.h>
13*4882a593Smuzhiyun #include <asm/arch-tegra/ap.h>
14*4882a593Smuzhiyun #include <asm/arch-tegra/tegra_i2c.h>
15*4882a593Smuzhiyun #include <asm/arch-tegra/sys_proto.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
18*4882a593Smuzhiyun #define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define VDD_CORE_NOMINAL_T20 0x16 /* 1.275v */
21*4882a593Smuzhiyun #define VDD_CPU_NOMINAL_T20 0x0f /* 1.1v */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define VDD_RELATION 0x02 /* 50mv */
24*4882a593Smuzhiyun #define VDD_TRANSITION_STEP 0x06 /* 150mv */
25*4882a593Smuzhiyun #define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
28*4882a593Smuzhiyun
pmu_set_nominal(void)29*4882a593Smuzhiyun int pmu_set_nominal(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct udevice *bus, *dev;
32*4882a593Smuzhiyun int core, cpu;
33*4882a593Smuzhiyun int ret;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* by default, the table has been filled with T25 settings */
36*4882a593Smuzhiyun switch (tegra_get_chip_sku()) {
37*4882a593Smuzhiyun case TEGRA_SOC_T20:
38*4882a593Smuzhiyun core = VDD_CORE_NOMINAL_T20;
39*4882a593Smuzhiyun cpu = VDD_CPU_NOMINAL_T20;
40*4882a593Smuzhiyun break;
41*4882a593Smuzhiyun case TEGRA_SOC_T25:
42*4882a593Smuzhiyun core = VDD_CORE_NOMINAL_T25;
43*4882a593Smuzhiyun cpu = VDD_CPU_NOMINAL_T25;
44*4882a593Smuzhiyun break;
45*4882a593Smuzhiyun default:
46*4882a593Smuzhiyun debug("%s: Unknown SKU id\n", __func__);
47*4882a593Smuzhiyun return -1;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun ret = tegra_i2c_get_dvc_bus(&bus);
51*4882a593Smuzhiyun if (ret) {
52*4882a593Smuzhiyun debug("%s: Cannot find DVC I2C bus\n", __func__);
53*4882a593Smuzhiyun return ret;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
56*4882a593Smuzhiyun if (ret) {
57*4882a593Smuzhiyun debug("%s: Cannot find DVC I2C chip\n", __func__);
58*4882a593Smuzhiyun return ret;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun tps6586x_init(dev);
62*4882a593Smuzhiyun tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
63*4882a593Smuzhiyun return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
64*4882a593Smuzhiyun VDD_TRANSITION_RATE, VDD_RELATION);
65*4882a593Smuzhiyun }
66