1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <asm/arch/tegra.h> 10*4882a593Smuzhiyun #include <asm/arch-tegra/pmc.h> 11*4882a593Smuzhiyun #include "../cpu.h" 12*4882a593Smuzhiyun enable_cpu_power_rail(void)13*4882a593Smuzhiyunstatic void enable_cpu_power_rail(void) 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 16*4882a593Smuzhiyun u32 reg; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reg = readl(&pmc->pmc_cntrl); 19*4882a593Smuzhiyun reg |= CPUPWRREQ_OE; 20*4882a593Smuzhiyun writel(reg, &pmc->pmc_cntrl); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * The TI PMU65861C needs a 3.75ms delay between enabling 24*4882a593Smuzhiyun * the power rail and enabling the CPU clock. This delay 25*4882a593Smuzhiyun * between SM1EN and SM1 is for switching time + the ramp 26*4882a593Smuzhiyun * up of the voltage to the CPU (VDD_CPU from PMU). 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun udelay(3750); 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun start_cpu(u32 reset_vector)31*4882a593Smuzhiyunvoid start_cpu(u32 reset_vector) 32*4882a593Smuzhiyun { 33*4882a593Smuzhiyun /* Enable VDD_CPU */ 34*4882a593Smuzhiyun enable_cpu_power_rail(); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Hold the CPUs in reset */ 37*4882a593Smuzhiyun reset_A9_cpu(1); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Disable the CPU clock */ 40*4882a593Smuzhiyun enable_cpu_clock(0); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Enable CoreSight */ 43*4882a593Smuzhiyun clock_enable_coresight(1); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Set the entry point for CPU execution from reset, 47*4882a593Smuzhiyun * if it's a non-zero value. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun if (reset_vector) 50*4882a593Smuzhiyun writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Enable the CPU clock */ 53*4882a593Smuzhiyun enable_cpu_clock(1); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* If the CPU doesn't already have power, power it up */ 56*4882a593Smuzhiyun powerup_cpu(); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Take the CPU out of reset */ 59*4882a593Smuzhiyun reset_A9_cpu(0); 60*4882a593Smuzhiyun } 61