1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <fdt_support.h>
9*4882a593Smuzhiyun #include <fdtdec.h>
10*4882a593Smuzhiyun #include <asm/arch/tegra.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun extern unsigned long nvtboot_boot_x0;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * We only support up to two banks since that's all the binary bootloader
20*4882a593Smuzhiyun * ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM above 4G.
21*4882a593Smuzhiyun * This is all a fairly safe assumption, since the L4T kernel makes the same
22*4882a593Smuzhiyun * assumptions, so the bootloader is unlikely to change.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * This is written to before relocation, and hence cannot be in .bss, since
25*4882a593Smuzhiyun * .bss overlaps the DTB that's appended to the U-Boot binary. The initializer
26*4882a593Smuzhiyun * forces this into .data and avoids this issue. This also has the nice side-
27*4882a593Smuzhiyun * effect of the content being valid after relocation.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun static struct {
30*4882a593Smuzhiyun u64 start;
31*4882a593Smuzhiyun u64 size;
32*4882a593Smuzhiyun } ram_banks[2] = {{1}};
33*4882a593Smuzhiyun
dram_init(void)34*4882a593Smuzhiyun int dram_init(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun unsigned int na, ns;
37*4882a593Smuzhiyun const void *nvtboot_blob = (void *)nvtboot_boot_x0;
38*4882a593Smuzhiyun int node, len, i;
39*4882a593Smuzhiyun const u32 *prop;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun memset(ram_banks, 0, sizeof(ram_banks));
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
44*4882a593Smuzhiyun ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun node = fdt_path_offset(nvtboot_blob, "/memory");
47*4882a593Smuzhiyun if (node < 0) {
48*4882a593Smuzhiyun pr_err("Can't find /memory node in nvtboot DTB");
49*4882a593Smuzhiyun hang();
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
52*4882a593Smuzhiyun if (!prop) {
53*4882a593Smuzhiyun pr_err("Can't find /memory/reg property in nvtboot DTB");
54*4882a593Smuzhiyun hang();
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun len /= (na + ns);
58*4882a593Smuzhiyun if (len > ARRAY_SIZE(ram_banks))
59*4882a593Smuzhiyun len = ARRAY_SIZE(ram_banks);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun gd->ram_size = 0;
62*4882a593Smuzhiyun for (i = 0; i < len; i++) {
63*4882a593Smuzhiyun ram_banks[i].start = fdt_read_number(prop, na);
64*4882a593Smuzhiyun prop += na;
65*4882a593Smuzhiyun ram_banks[i].size = fdt_read_number(prop, ns);
66*4882a593Smuzhiyun prop += ns;
67*4882a593Smuzhiyun gd->ram_size += ram_banks[i].size;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun extern unsigned long nvtboot_boot_x0;
74*4882a593Smuzhiyun
dram_init_banksize(void)75*4882a593Smuzhiyun int dram_init_banksize(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int i;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun for (i = 0; i < 2; i++) {
80*4882a593Smuzhiyun gd->bd->bi_dram[i].start = ram_banks[i].start;
81*4882a593Smuzhiyun gd->bd->bi_dram[i].size = ram_banks[i].size;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
board_get_usable_ram_top(ulong total_size)87*4882a593Smuzhiyun ulong board_get_usable_ram_top(ulong total_size)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun return ram_banks[0].start + ram_banks[0].size;
90*4882a593Smuzhiyun }
91