1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2016, NVIDIA CORPORATION. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <config.h> 8*4882a593Smuzhiyun#include <linux/linkage.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#define SMC_SIP_INVOKE_MCE 0x82FFFF00 11*4882a593Smuzhiyun#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) 12*4882a593Smuzhiyun#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14) 13*4882a593Smuzhiyun#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15) 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunENTRY(__asm_tegra_cache_smc) 16*4882a593Smuzhiyun mov x1, #0 17*4882a593Smuzhiyun mov x2, #0 18*4882a593Smuzhiyun mov x3, #0 19*4882a593Smuzhiyun mov x4, #0 20*4882a593Smuzhiyun mov x5, #0 21*4882a593Smuzhiyun mov x6, #0 22*4882a593Smuzhiyun smc #0 23*4882a593Smuzhiyun mov x0, #0 24*4882a593Smuzhiyun ret 25*4882a593SmuzhiyunENDPROC(__asm_invalidate_l3_dcache) 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunENTRY(__asm_invalidate_l3_dcache) 28*4882a593Smuzhiyun mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff) 29*4882a593Smuzhiyun movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16 30*4882a593Smuzhiyun b __asm_tegra_cache_smc 31*4882a593SmuzhiyunENDPROC(__asm_invalidate_l3_dcache) 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunENTRY(__asm_flush_l3_dcache) 34*4882a593Smuzhiyun mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff) 35*4882a593Smuzhiyun movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16 36*4882a593Smuzhiyun b __asm_tegra_cache_smc 37*4882a593SmuzhiyunENDPROC(__asm_flush_l3_dcache) 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunENTRY(__asm_invalidate_l3_icache) 40*4882a593Smuzhiyun mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) 41*4882a593Smuzhiyun movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 42*4882a593Smuzhiyun b __asm_tegra_cache_smc 43*4882a593SmuzhiyunENDPROC(__asm_invalidate_l3_icache) 44