1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2013
3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /* Tegra124 high-level function multiplexing */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/arch/clock.h>
12*4882a593Smuzhiyun #include <asm/arch/funcmux.h>
13*4882a593Smuzhiyun #include <asm/arch/pinmux.h>
14*4882a593Smuzhiyun
funcmux_select(enum periph_id id,int config)15*4882a593Smuzhiyun int funcmux_select(enum periph_id id, int config)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun int bad_config = config != FUNCMUX_DEFAULT;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun switch (id) {
20*4882a593Smuzhiyun case PERIPH_ID_UART4:
21*4882a593Smuzhiyun switch (config) {
22*4882a593Smuzhiyun case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
23*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
24*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
25*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
26*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
29*4882a593Smuzhiyun pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
30*4882a593Smuzhiyun pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
31*4882a593Smuzhiyun pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_PJ7);
34*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_PB0);
35*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_PB1);
36*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_PK7);
37*4882a593Smuzhiyun break;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun break;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun case PERIPH_ID_UART1:
42*4882a593Smuzhiyun switch (config) {
43*4882a593Smuzhiyun case FUNCMUX_UART1_KBC:
44*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
45*4882a593Smuzhiyun PMUX_FUNC_UARTA);
46*4882a593Smuzhiyun pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
47*4882a593Smuzhiyun PMUX_FUNC_UARTA);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
50*4882a593Smuzhiyun pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
53*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Add other periph IDs here as needed */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun default:
61*4882a593Smuzhiyun debug("%s: invalid periph_id %d", __func__, id);
62*4882a593Smuzhiyun return -1;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (bad_config) {
66*4882a593Smuzhiyun debug("%s: invalid config %d for periph_id %d", __func__,
67*4882a593Smuzhiyun config, id);
68*4882a593Smuzhiyun return -1;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
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