1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * SoC-specific setup info 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2010,2011 5*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <config.h> 11*4882a593Smuzhiyun#include <linux/linkage.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#ifdef CONFIG_ARM64 14*4882a593Smuzhiyun .align 5 15*4882a593SmuzhiyunENTRY(reset_cpu) 16*4882a593Smuzhiyun /* get address for global reset register */ 17*4882a593Smuzhiyun ldr x1, =PRM_RSTCTRL 18*4882a593Smuzhiyun ldr w3, [x1] 19*4882a593Smuzhiyun /* force reset */ 20*4882a593Smuzhiyun orr w3, w3, #0x10 21*4882a593Smuzhiyun str w3, [x1] 22*4882a593Smuzhiyun mov w0, w0 23*4882a593Smuzhiyun1: 24*4882a593Smuzhiyun b 1b 25*4882a593SmuzhiyunENDPROC(reset_cpu) 26*4882a593Smuzhiyun#else 27*4882a593Smuzhiyun .align 5 28*4882a593SmuzhiyunENTRY(reset_cpu) 29*4882a593Smuzhiyun ldr r1, rstctl @ get addr for global reset 30*4882a593Smuzhiyun @ reg 31*4882a593Smuzhiyun ldr r3, [r1] 32*4882a593Smuzhiyun orr r3, r3, #0x10 33*4882a593Smuzhiyun str r3, [r1] @ force reset 34*4882a593Smuzhiyun mov r0, r0 35*4882a593Smuzhiyun_loop_forever: 36*4882a593Smuzhiyun b _loop_forever 37*4882a593Smuzhiyunrstctl: 38*4882a593Smuzhiyun .word PRM_RSTCTRL 39*4882a593SmuzhiyunENDPROC(reset_cpu) 40*4882a593Smuzhiyun#endif 41