1 /*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 /* Tegra vpr routines */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch/mc.h>
13
14 #include <fdt_support.h>
15
16 static bool _configured;
17
tegra_gpu_config(void)18 void tegra_gpu_config(void)
19 {
20 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
21
22 /* Turn VPR off */
23 writel(0, &mc->mc_video_protect_size_mb);
24 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
25 &mc->mc_video_protect_reg_ctrl);
26 /* read back to ensure the write went through */
27 readl(&mc->mc_video_protect_reg_ctrl);
28
29 debug("configured VPR\n");
30
31 _configured = true;
32 }
33
34 #if defined(CONFIG_OF_LIBFDT)
35
tegra_gpu_enable_node(void * blob,const char * compat)36 int tegra_gpu_enable_node(void *blob, const char *compat)
37 {
38 int offset;
39
40 if (!_configured)
41 return 0;
42
43 offset = fdt_node_offset_by_compatible(blob, -1, compat);
44 while (offset != -FDT_ERR_NOTFOUND) {
45 fdt_status_okay(blob, offset);
46 offset = fdt_node_offset_by_compatible(blob, offset, compat);
47 }
48
49 return 0;
50 }
51
52 #endif
53