1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /* Tegra vpr routines */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/tegra.h>
12*4882a593Smuzhiyun #include <asm/arch/mc.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <fdt_support.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static bool _configured;
17*4882a593Smuzhiyun
tegra_gpu_config(void)18*4882a593Smuzhiyun void tegra_gpu_config(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Turn VPR off */
23*4882a593Smuzhiyun writel(0, &mc->mc_video_protect_size_mb);
24*4882a593Smuzhiyun writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
25*4882a593Smuzhiyun &mc->mc_video_protect_reg_ctrl);
26*4882a593Smuzhiyun /* read back to ensure the write went through */
27*4882a593Smuzhiyun readl(&mc->mc_video_protect_reg_ctrl);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun debug("configured VPR\n");
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun _configured = true;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #if defined(CONFIG_OF_LIBFDT)
35*4882a593Smuzhiyun
tegra_gpu_enable_node(void * blob,const char * compat)36*4882a593Smuzhiyun int tegra_gpu_enable_node(void *blob, const char *compat)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun int offset;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if (!_configured)
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun offset = fdt_node_offset_by_compatible(blob, -1, compat);
44*4882a593Smuzhiyun while (offset != -FDT_ERR_NOTFOUND) {
45*4882a593Smuzhiyun fdt_status_okay(blob, offset);
46*4882a593Smuzhiyun offset = fdt_node_offset_by_compatible(blob, offset, compat);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #endif
53