1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include "emc.h" 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/arch/clock.h> 11*4882a593Smuzhiyun #include <asm/arch/emc.h> 12*4882a593Smuzhiyun #include <asm/arch/pmu.h> 13*4882a593Smuzhiyun #include <asm/arch/tegra.h> 14*4882a593Smuzhiyun #include <asm/arch-tegra/ap.h> 15*4882a593Smuzhiyun #include <asm/arch-tegra/clk_rst.h> 16*4882a593Smuzhiyun #include <asm/arch-tegra/sys_proto.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* These rates are hard-coded for now, until fdt provides them */ 21*4882a593Smuzhiyun #define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) 22*4882a593Smuzhiyun #define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) 23*4882a593Smuzhiyun board_emc_init(void)24*4882a593Smuzhiyunint board_emc_init(void) 25*4882a593Smuzhiyun { 26*4882a593Smuzhiyun unsigned rate; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun switch (tegra_get_chip_sku()) { 29*4882a593Smuzhiyun default: 30*4882a593Smuzhiyun case TEGRA_SOC_T20: 31*4882a593Smuzhiyun rate = EMC_SDRAM_RATE_T20; 32*4882a593Smuzhiyun break; 33*4882a593Smuzhiyun case TEGRA_SOC_T25: 34*4882a593Smuzhiyun rate = EMC_SDRAM_RATE_T25; 35*4882a593Smuzhiyun break; 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun return tegra_set_emc(gd->fdt_blob, rate); 38*4882a593Smuzhiyun } 39