1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010-2015 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #include <asm/types.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Stabilization delays, in usec */ 10*4882a593Smuzhiyun #define PLL_STABILIZATION_DELAY (300) 11*4882a593Smuzhiyun #define IO_STABILIZATION_DELAY (1000) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #if defined(CONFIG_TEGRA20) 14*4882a593Smuzhiyun #define NVBL_PLLP_KHZ 216000 15*4882a593Smuzhiyun #define CSITE_KHZ 144000 16*4882a593Smuzhiyun #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ 17*4882a593Smuzhiyun defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) 18*4882a593Smuzhiyun #define NVBL_PLLP_KHZ 408000 19*4882a593Smuzhiyun #define CSITE_KHZ 136000 20*4882a593Smuzhiyun #else 21*4882a593Smuzhiyun #error "Unknown Tegra chip!" 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PLLX_ENABLED (1 << 30) 25*4882a593Smuzhiyun #define CCLK_BURST_POLICY 0x20008888 26*4882a593Smuzhiyun #define SUPER_CCLK_DIVIDER 0x80000000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Calculate clock fractional divider value from ref and target frequencies */ 29*4882a593Smuzhiyun #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Calculate clock frequency value from reference and clock divider value */ 32*4882a593Smuzhiyun #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* AVP/CPU ID */ 35*4882a593Smuzhiyun #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ 36*4882a593Smuzhiyun #define PG_UP_TAG_0 0x0 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CORESIGHT_UNLOCK 0xC5ACCE55 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) 41*4882a593Smuzhiyun #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) 42*4882a593Smuzhiyun #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) 43*4882a593Smuzhiyun #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0) 44*4882a593Smuzhiyun #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) 47*4882a593Smuzhiyun #define FLOW_MODE_STOP 2 48*4882a593Smuzhiyun #define HALT_COP_EVENT_JTAG (1 << 28) 49*4882a593Smuzhiyun #define HALT_COP_EVENT_IRQ_1 (1 << 11) 50*4882a593Smuzhiyun #define HALT_COP_EVENT_FIQ_1 (1 << 9) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define FLOW_MODE_NONE 0 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */ 57*4882a593Smuzhiyun #define SB_AA64_RESET_LOW 0x6000C230 58*4882a593Smuzhiyun #define SB_AA64_RESET_HIGH 0x6000C234 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct clk_pll_table { 61*4882a593Smuzhiyun u16 n; 62*4882a593Smuzhiyun u16 m; 63*4882a593Smuzhiyun u8 p; 64*4882a593Smuzhiyun u8 cpcon; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun void clock_enable_coresight(int enable); 68*4882a593Smuzhiyun void enable_cpu_clock(int enable); 69*4882a593Smuzhiyun void halt_avp(void) __attribute__ ((noreturn)); 70*4882a593Smuzhiyun void init_pllx(void); 71*4882a593Smuzhiyun void powerup_cpu(void); 72*4882a593Smuzhiyun void reset_A9_cpu(int reset); 73*4882a593Smuzhiyun void start_cpu(u32 reset_vector); 74*4882a593Smuzhiyun int tegra_get_chip(void); 75*4882a593Smuzhiyun int tegra_get_sku_info(void); 76*4882a593Smuzhiyun int tegra_get_chip_sku(void); 77*4882a593Smuzhiyun void adjust_pllp_out_freqs(void); 78*4882a593Smuzhiyun void pmic_enable_cpu_vdd(void); 79