1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 - 2015 Xilinx, Inc. 3*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com> 4*4882a593Smuzhiyun * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <common.h> 12*4882a593Smuzhiyun #include <asm/system.h> 13*4882a593Smuzhiyun #include <asm/armv8/mmu.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun static struct mm_region tegra_mem_map[] = { 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun .virt = 0x0UL, 18*4882a593Smuzhiyun .phys = 0x0UL, 19*4882a593Smuzhiyun .size = 0x80000000UL, 20*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 21*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE | 22*4882a593Smuzhiyun PTE_BLOCK_PXN | PTE_BLOCK_UXN 23*4882a593Smuzhiyun }, { 24*4882a593Smuzhiyun .virt = 0x80000000UL, 25*4882a593Smuzhiyun .phys = 0x80000000UL, 26*4882a593Smuzhiyun .size = 0x80000000UL, 27*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 28*4882a593Smuzhiyun PTE_BLOCK_INNER_SHARE 29*4882a593Smuzhiyun }, { 30*4882a593Smuzhiyun /* List terminator */ 31*4882a593Smuzhiyun 0, 32*4882a593Smuzhiyun } 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct mm_region *mem_map = tegra_mem_map; 36