1*4882a593Smuzhiyun@ 2*4882a593Smuzhiyun@ ARMv8 RMR reset sequence on Allwinner SoCs. 3*4882a593Smuzhiyun@ 4*4882a593Smuzhiyun@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to 5*4882a593Smuzhiyun@ exectute the Boot ROM in this state), so we need to switch to AArch64 6*4882a593Smuzhiyun@ at some point. 7*4882a593Smuzhiyun@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register 8*4882a593Smuzhiyun@ (RMR), which triggers a warm-reset of a core and can request to switch 9*4882a593Smuzhiyun@ into a different execution state (AArch32 or AArch64). 10*4882a593Smuzhiyun@ The address at which execution starts after the reset is held in the 11*4882a593Smuzhiyun@ RVBAR system register, which is architecturally read-only. 12*4882a593Smuzhiyun@ Allwinner provides a writable alias of this register in MMIO space, so 13*4882a593Smuzhiyun@ we can easily set the start address of AArch64 code. 14*4882a593Smuzhiyun@ This code below switches to AArch64 and starts execution at the specified 15*4882a593Smuzhiyun@ start address. It needs to be assembled by an ARM(32) assembler and 16*4882a593Smuzhiyun@ the machine code must be inserted as verbatim .word statements into the 17*4882a593Smuzhiyun@ beginning of the AArch64 U-Boot code. 18*4882a593Smuzhiyun@ To get the encoded bytes, use: 19*4882a593Smuzhiyun@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S 20*4882a593Smuzhiyun@ ${CROSS_COMPILE}objdump -d rmr_switch.o 21*4882a593Smuzhiyun@ 22*4882a593Smuzhiyun@ The resulting words should be inserted into the U-Boot file at 23*4882a593Smuzhiyun@ arch/arm/include/asm/arch-sunxi/boot0.h. 24*4882a593Smuzhiyun@ 25*4882a593Smuzhiyun@ This file is not build by the U-Boot build system, but provided only as a 26*4882a593Smuzhiyun@ reference and to be able to regenerate a (probably fixed) version of this 27*4882a593Smuzhiyun@ code found in encoded form in boot0.h. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun.text 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register 32*4882a593Smuzhiyun ldr r0, =0x57aA7add @ start address, to be replaced 33*4882a593Smuzhiyun str r0, [r1] 34*4882a593Smuzhiyun dsb sy 35*4882a593Smuzhiyun isb sy 36*4882a593Smuzhiyun mrc 15, 0, r0, cr12, cr0, 2 @ read RMR register 37*4882a593Smuzhiyun orr r0, r0, #3 @ request reset in AArch64 38*4882a593Smuzhiyun mcr 15, 0, r0, cr12, cr0, 2 @ write RMR register 39*4882a593Smuzhiyun isb sy 40*4882a593Smuzhiyun1: wfi 41*4882a593Smuzhiyun b 1b 42