1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Sunxi PMIC bus access helpers
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * The axp152 & axp209 use an i2c bus, the axp221 uses the p2wi bus and the
7*4882a593Smuzhiyun * axp223 uses the rsb bus, these functions abstract this.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/arch/p2wi.h>
14*4882a593Smuzhiyun #include <asm/arch/rsb.h>
15*4882a593Smuzhiyun #include <i2c.h>
16*4882a593Smuzhiyun #include <asm/arch/pmic_bus.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define AXP152_I2C_ADDR 0x30
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define AXP209_I2C_ADDR 0x34
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define AXP221_CHIP_ADDR 0x68
23*4882a593Smuzhiyun #define AXP221_CTRL_ADDR 0x3e
24*4882a593Smuzhiyun #define AXP221_INIT_DATA 0x3e
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* AXP818 device and runtime addresses are same as AXP223 */
27*4882a593Smuzhiyun #define AXP223_DEVICE_ADDR 0x3a3
28*4882a593Smuzhiyun #define AXP223_RUNTIME_ADDR 0x2d
29*4882a593Smuzhiyun
pmic_bus_init(void)30*4882a593Smuzhiyun int pmic_bus_init(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun /* This cannot be 0 because it is used in SPL before BSS is ready */
33*4882a593Smuzhiyun static int needs_init = 1;
34*4882a593Smuzhiyun __maybe_unused int ret;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (!needs_init)
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
40*4882a593Smuzhiyun # ifdef CONFIG_MACH_SUN6I
41*4882a593Smuzhiyun p2wi_init();
42*4882a593Smuzhiyun ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
43*4882a593Smuzhiyun AXP221_INIT_DATA);
44*4882a593Smuzhiyun # elif defined CONFIG_MACH_SUN8I_R40
45*4882a593Smuzhiyun /* Nothing. R40 uses the AXP221s in I2C mode */
46*4882a593Smuzhiyun ret = 0;
47*4882a593Smuzhiyun # else
48*4882a593Smuzhiyun ret = rsb_init();
49*4882a593Smuzhiyun if (ret)
50*4882a593Smuzhiyun return ret;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
53*4882a593Smuzhiyun # endif
54*4882a593Smuzhiyun if (ret)
55*4882a593Smuzhiyun return ret;
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun needs_init = 0;
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
pmic_bus_read(u8 reg,u8 * data)62*4882a593Smuzhiyun int pmic_bus_read(u8 reg, u8 *data)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun #ifdef CONFIG_AXP152_POWER
65*4882a593Smuzhiyun return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
66*4882a593Smuzhiyun #elif defined CONFIG_AXP209_POWER
67*4882a593Smuzhiyun return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
68*4882a593Smuzhiyun #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
69*4882a593Smuzhiyun # ifdef CONFIG_MACH_SUN6I
70*4882a593Smuzhiyun return p2wi_read(reg, data);
71*4882a593Smuzhiyun # elif defined CONFIG_MACH_SUN8I_R40
72*4882a593Smuzhiyun return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
73*4882a593Smuzhiyun # else
74*4882a593Smuzhiyun return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
75*4882a593Smuzhiyun # endif
76*4882a593Smuzhiyun #endif
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
pmic_bus_write(u8 reg,u8 data)79*4882a593Smuzhiyun int pmic_bus_write(u8 reg, u8 data)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun #ifdef CONFIG_AXP152_POWER
82*4882a593Smuzhiyun return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
83*4882a593Smuzhiyun #elif defined CONFIG_AXP209_POWER
84*4882a593Smuzhiyun return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
85*4882a593Smuzhiyun #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
86*4882a593Smuzhiyun # ifdef CONFIG_MACH_SUN6I
87*4882a593Smuzhiyun return p2wi_write(reg, data);
88*4882a593Smuzhiyun # elif defined CONFIG_MACH_SUN8I_R40
89*4882a593Smuzhiyun return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
90*4882a593Smuzhiyun # else
91*4882a593Smuzhiyun return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
92*4882a593Smuzhiyun # endif
93*4882a593Smuzhiyun #endif
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
pmic_bus_setbits(u8 reg,u8 bits)96*4882a593Smuzhiyun int pmic_bus_setbits(u8 reg, u8 bits)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun int ret;
99*4882a593Smuzhiyun u8 val;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun ret = pmic_bus_read(reg, &val);
102*4882a593Smuzhiyun if (ret)
103*4882a593Smuzhiyun return ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun val |= bits;
106*4882a593Smuzhiyun return pmic_bus_write(reg, val);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
pmic_bus_clrbits(u8 reg,u8 bits)109*4882a593Smuzhiyun int pmic_bus_clrbits(u8 reg, u8 bits)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun int ret;
112*4882a593Smuzhiyun u8 val;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun ret = pmic_bus_read(reg, &val);
115*4882a593Smuzhiyun if (ret)
116*4882a593Smuzhiyun return ret;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun val &= ~bits;
119*4882a593Smuzhiyun return pmic_bus_write(reg, val);
120*4882a593Smuzhiyun }
121