1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007-2011
3*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4*4882a593Smuzhiyun * Tom Cubie <tangliang@allwinnertech.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch/gpio.h>
12*4882a593Smuzhiyun
sunxi_gpio_set_cfgbank(struct sunxi_gpio * pio,int bank_offset,u32 val)13*4882a593Smuzhiyun void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun u32 index = GPIO_CFG_INDEX(bank_offset);
16*4882a593Smuzhiyun u32 offset = GPIO_CFG_OFFSET(bank_offset);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
19*4882a593Smuzhiyun }
20*4882a593Smuzhiyun
sunxi_gpio_set_cfgpin(u32 pin,u32 val)21*4882a593Smuzhiyun void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun u32 bank = GPIO_BANK(pin);
24*4882a593Smuzhiyun struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun sunxi_gpio_set_cfgbank(pio, pin, val);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
sunxi_gpio_get_cfgbank(struct sunxi_gpio * pio,int bank_offset)29*4882a593Smuzhiyun int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun u32 index = GPIO_CFG_INDEX(bank_offset);
32*4882a593Smuzhiyun u32 offset = GPIO_CFG_OFFSET(bank_offset);
33*4882a593Smuzhiyun u32 cfg;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun cfg = readl(&pio->cfg[0] + index);
36*4882a593Smuzhiyun cfg >>= offset;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return cfg & 0xf;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
sunxi_gpio_get_cfgpin(u32 pin)41*4882a593Smuzhiyun int sunxi_gpio_get_cfgpin(u32 pin)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun u32 bank = GPIO_BANK(pin);
44*4882a593Smuzhiyun struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return sunxi_gpio_get_cfgbank(pio, pin);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
sunxi_gpio_set_drv(u32 pin,u32 val)49*4882a593Smuzhiyun int sunxi_gpio_set_drv(u32 pin, u32 val)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun u32 bank = GPIO_BANK(pin);
52*4882a593Smuzhiyun u32 index = GPIO_DRV_INDEX(pin);
53*4882a593Smuzhiyun u32 offset = GPIO_DRV_OFFSET(pin);
54*4882a593Smuzhiyun struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
sunxi_gpio_set_pull(u32 pin,u32 val)61*4882a593Smuzhiyun int sunxi_gpio_set_pull(u32 pin, u32 val)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun u32 bank = GPIO_BANK(pin);
64*4882a593Smuzhiyun u32 index = GPIO_PULL_INDEX(pin);
65*4882a593Smuzhiyun u32 offset = GPIO_PULL_OFFSET(pin);
66*4882a593Smuzhiyun struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun }
72