1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Sunxi A31 Power Management Unit
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
5*4882a593Smuzhiyun * http://linux-sunxi.org
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * (C) Copyright 2006-2013
10*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
11*4882a593Smuzhiyun * Berg Xing <bergxing@allwinnertech.com>
12*4882a593Smuzhiyun * Tom Cubie <tangliang@allwinnertech.com>
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <errno.h>
19*4882a593Smuzhiyun #include <asm/io.h>
20*4882a593Smuzhiyun #include <asm/arch/cpu.h>
21*4882a593Smuzhiyun #include <asm/arch/gpio.h>
22*4882a593Smuzhiyun #include <asm/arch/p2wi.h>
23*4882a593Smuzhiyun #include <asm/arch/prcm.h>
24*4882a593Smuzhiyun #include <asm/arch/clock.h>
25*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
26*4882a593Smuzhiyun
p2wi_init(void)27*4882a593Smuzhiyun void p2wi_init(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Enable p2wi and PIO clk, and de-assert their resets */
32*4882a593Smuzhiyun prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
35*4882a593Smuzhiyun sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
38*4882a593Smuzhiyun writel(P2WI_CTRL_RESET, &p2wi->ctrl);
39*4882a593Smuzhiyun sdelay(0x100);
40*4882a593Smuzhiyun writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
41*4882a593Smuzhiyun &p2wi->cc);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
p2wi_change_to_p2wi_mode(u8 slave_addr,u8 ctrl_reg,u8 init_data)44*4882a593Smuzhiyun int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
47*4882a593Smuzhiyun unsigned long tmo = timer_get_us() + 1000000;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun writel(P2WI_PM_DEV_ADDR(slave_addr) |
50*4882a593Smuzhiyun P2WI_PM_CTRL_ADDR(ctrl_reg) |
51*4882a593Smuzhiyun P2WI_PM_INIT_DATA(init_data) |
52*4882a593Smuzhiyun P2WI_PM_INIT_SEND,
53*4882a593Smuzhiyun &p2wi->pm);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
56*4882a593Smuzhiyun if (timer_get_us() > tmo)
57*4882a593Smuzhiyun return -ETIME;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
p2wi_await_trans(void)63*4882a593Smuzhiyun static int p2wi_await_trans(void)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
66*4882a593Smuzhiyun unsigned long tmo = timer_get_us() + 1000000;
67*4882a593Smuzhiyun int ret;
68*4882a593Smuzhiyun u8 reg;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun while (1) {
71*4882a593Smuzhiyun reg = readl(&p2wi->status);
72*4882a593Smuzhiyun if (reg & P2WI_STAT_TRANS_ERR) {
73*4882a593Smuzhiyun ret = -EIO;
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun if (reg & P2WI_STAT_TRANS_DONE) {
77*4882a593Smuzhiyun ret = 0;
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun if (timer_get_us() > tmo) {
81*4882a593Smuzhiyun ret = -ETIME;
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun writel(reg, &p2wi->status); /* Clear status bits */
86*4882a593Smuzhiyun return ret;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
p2wi_read(const u8 addr,u8 * data)89*4882a593Smuzhiyun int p2wi_read(const u8 addr, u8 *data)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
92*4882a593Smuzhiyun int ret;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
95*4882a593Smuzhiyun writel(P2WI_DATA_NUM_BYTES(1) |
96*4882a593Smuzhiyun P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
97*4882a593Smuzhiyun writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
98*4882a593Smuzhiyun writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = p2wi_await_trans();
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
103*4882a593Smuzhiyun return ret;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
p2wi_write(const u8 addr,u8 data)106*4882a593Smuzhiyun int p2wi_write(const u8 addr, u8 data)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
111*4882a593Smuzhiyun writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
112*4882a593Smuzhiyun writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
113*4882a593Smuzhiyun writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
114*4882a593Smuzhiyun writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun return p2wi_await_trans();
117*4882a593Smuzhiyun }
118