1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * GTBUS initialisation for sun9i
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
5*4882a593Smuzhiyun * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/gtbus_sun9i.h>
13*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
16*4882a593Smuzhiyun
gtbus_init(void)17*4882a593Smuzhiyun void gtbus_init(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun struct sunxi_gtbus_reg * const gtbus =
20*4882a593Smuzhiyun (struct sunxi_gtbus_reg *)SUNXI_GTBUS_BASE;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * We use the same setting that Allwinner used in Boot0 for now.
24*4882a593Smuzhiyun * It may be advantageous to adjust these for various workloads
25*4882a593Smuzhiyun * (e.g. headless use cases that focus on IO throughput).
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun writel((GT_PRIO_HIGH << GT_PORT_FE0) |
28*4882a593Smuzhiyun (GT_PRIO_HIGH << GT_PORT_BE1) |
29*4882a593Smuzhiyun (GT_PRIO_HIGH << GT_PORT_BE2) |
30*4882a593Smuzhiyun (GT_PRIO_HIGH << GT_PORT_IEP0) |
31*4882a593Smuzhiyun (GT_PRIO_HIGH << GT_PORT_FE1) |
32*4882a593Smuzhiyun (GT_PRIO_HIGH << GT_PORT_BE0) |
33*4882a593Smuzhiyun (GT_PRIO_HIGH << GT_PORT_FE2) |
34*4882a593Smuzhiyun (GT_PRIO_HIGH << GT_PORT_IEP1),
35*4882a593Smuzhiyun >bus->mst_read_prio_cfg[0]);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
38*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
39*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE1]);
40*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE2]);
41*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP0]);
42*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE1]);
43*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE0]);
44*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE2]);
45*4882a593Smuzhiyun writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP1]);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #endif
49