1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * DRAM init helper functions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <asm/barriers.h> 11*4882a593Smuzhiyun #include <asm/io.h> 12*4882a593Smuzhiyun #include <asm/arch/dram.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Wait up to 1s for value to be set in given part of reg. 16*4882a593Smuzhiyun */ mctl_await_completion(u32 * reg,u32 mask,u32 val)17*4882a593Smuzhiyunvoid mctl_await_completion(u32 *reg, u32 mask, u32 val) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun unsigned long tmo = timer_get_us() + 1000000; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun while ((readl(reg) & mask) != val) { 22*4882a593Smuzhiyun if (timer_get_us() > tmo) 23*4882a593Smuzhiyun panic("Timeout initialising DRAM\n"); 24*4882a593Smuzhiyun } 25*4882a593Smuzhiyun } 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Test if memory at offset offset matches memory at begin of DRAM 29*4882a593Smuzhiyun */ mctl_mem_matches(u32 offset)30*4882a593Smuzhiyunbool mctl_mem_matches(u32 offset) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun /* Try to write different values to RAM at two addresses */ 33*4882a593Smuzhiyun writel(0, CONFIG_SYS_SDRAM_BASE); 34*4882a593Smuzhiyun writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); 35*4882a593Smuzhiyun dsb(); 36*4882a593Smuzhiyun /* Check if the same value is actually observed when reading back */ 37*4882a593Smuzhiyun return readl(CONFIG_SYS_SDRAM_BASE) == 38*4882a593Smuzhiyun readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); 39*4882a593Smuzhiyun } 40